Top Tagged

Controlling the BRAM voltage supply for ZCU104 - ( ‎01-23-2021 08:35 AM )

by on Latest post on by

2 Replies 147 Views

True quad port ram vhdl - ( ‎01-17-2021 05:32 AM )

by on Latest post on by

5 Replies 275 Views

Bram initilization using .mem file - ( ‎12-17-2020 11:50 AM )

by on Latest post on by

4 Replies 311 Views

Write and read from one single port BRAM to anothe... - ( ‎12-04-2020 03:50 AM )

by on Latest post on by

4 Replies 304 Views

Simulating inferred BRAM - ( ‎11-16-2020 10:36 AM )

by on Latest post on by

2 Replies 316 Views

Custom IP with master AXI Lite - ( ‎10-08-2020 05:53 AM )

by on Latest post on by

10 Replies 1038 Views

When I convert a True Dual Port BRAM to a Single P... - ( ‎10-06-2020 01:59 PM )

by on Latest post on by

1 Reply 258 Views

How to triplicate program across BRAMs? - ( ‎10-03-2020 03:23 PM )

by on Latest post on by

4 Replies 508 Views

[Place 30-859] Some BRAM area constraints are over... - ( ‎09-20-2020 08:19 PM )

by on Latest post on by

1 Reply 381 Views

Ps-PL interface. Finding a way to move large amoun... - ( ‎09-18-2020 06:13 PM )

by on Latest post on by

18 Replies 934 Views

Bug in RAMB36E1 Verilog template (vivado/2017.2) - ( ‎09-08-2020 02:40 AM )

by on

0 Replies 365 Views

Low latency data transfer between PS-PL - ( ‎08-13-2020 11:38 AM )

by on

0 Replies 315 Views

How do I write binary file or text file with data ... - ( ‎07-14-2020 10:54 AM )

by on Latest post on by

1 Reply 331 Views

Help with accessing wide data width BRAM from PS t... - ( ‎05-27-2020 05:10 PM )

by on Latest post on by

5 Replies 671 Views

Post Implementation Simulation - BRAM data out one... - ( ‎05-19-2020 11:24 PM )

by on Latest post on by

8 Replies 666 Views

why UltraScale Memory Resources are 36K? - ( ‎05-14-2020 02:55 AM )

by on Latest post on by

1 Reply 470 Views

Re: Multichannel BRAM in Vivado IP Packager - ( ‎05-13-2020 06:52 AM )

by on

0 Replies 401 Views

Memory block ram in Vivado - ( ‎04-17-2020 11:44 AM )

by on Latest post on by

5 Replies 918 Views

Create BRAM utilization report based on BRAM(8k) x... - ( ‎04-09-2020 07:53 AM )

by on Latest post on by

4 Replies 971 Views

[Place 30-859] Some BRAM area constraints are over... - ( ‎04-08-2020 06:28 AM )

by on Latest post on by

8 Replies 1219 Views

Is BRAMs content persistant between kernel calls? - ( ‎03-11-2020 06:53 AM )

by on

0 Replies 275 Views

Bram Utilization - ( ‎01-15-2020 07:21 PM )

by on Latest post on by

4 Replies 457 Views

Unexpected BRAM utilization - ( ‎01-01-2020 07:20 AM )

by on Latest post on by

11 Replies 1035 Views

Cannot use output registers of BRAM - ( ‎12-28-2019 09:24 AM )

by on Latest post on by

6 Replies 729 Views

$recrem and $setuphold warnings - ( ‎12-24-2019 04:47 AM )

by on

0 Replies 597 Views

Block memory generator as Standalone ROM unpredic... - ( ‎10-25-2019 04:38 AM )

by on

0 Replies 446 Views

XPM FIFO MACRO, how is FIFO being realized when FI... - ( ‎10-18-2019 11:30 AM )

by on Latest post on by

2 Replies 914 Views

update_mem failed, Unknown Exception - ( ‎10-14-2019 05:24 AM )

by on Latest post on by

3 Replies 549 Views

Updatemem not updating the BRAM - ( ‎10-10-2019 08:32 AM )

by on Latest post on by

1 Reply 547 Views

VivadoHLS Cannot parallelize operations on indepen... - ( ‎09-29-2019 10:02 PM )

by on Latest post on by

8 Replies 1155 Views

Accessing BRAM in Linux Kernel hang - ( ‎09-25-2019 06:07 PM )

by on Latest post on by

5 Replies 934 Views

"Full" and "Empty" thresholds for cascaded FIFO36E... - ( ‎09-24-2019 07:47 AM )

by on Latest post on by

1 Reply 489 Views

XL6LX45T-3CSG324I Technical Issue - ( ‎09-17-2019 05:23 AM )

by on

0 Replies 376 Views

BRAM - ( ‎08-19-2019 03:04 PM )

by on Latest post on by

6 Replies 959 Views

updatemem XPM sets everything to zero - ( ‎07-30-2019 02:45 AM )

by on Latest post on by

1 Reply 712 Views

ZU+ FSBL fails to access BRAM on "cold" start - ( ‎07-25-2019 02:32 PM )

by on Latest post on by

4 Replies 703 Views

Synthesize IO arrays to BRAM blocks with pipelined... - ( ‎07-22-2019 11:21 PM )

by on Latest post on by

6 Replies 1479 Views

Vivado .MMI file generation bug - ( ‎07-12-2019 04:06 AM )

by on

0 Replies 653 Views

How to read BRAM data through ethernet using lwIP ... - ( ‎07-01-2019 11:24 PM )

by on Latest post on by

1 Reply 555 Views

Re: Where can I find the read (receive) and write ... - ( ‎06-20-2019 12:36 AM )

by on

0 Replies 631 Views

Re: Where can I find the read (receive) and write ... - ( ‎06-18-2019 11:53 PM )

by on

0 Replies 649 Views

updatemem to change the memory contents of an arbi... - ( ‎06-11-2019 06:11 AM )

by on Latest post on by

12 Replies 2017 Views

How do we implement crossbar/arbiter in the HLS C ... - ( ‎05-08-2019 11:33 PM )

by on Latest post on by

1 Reply 776 Views

How to write to different banks of BRAM simultaneo... - ( ‎05-06-2019 07:30 PM )

by on Latest post on by

6 Replies 1361 Views

Loss of BRAMs in Pblock - ( ‎04-11-2019 10:22 AM )

by on Latest post on by

1 Reply 979 Views

Runtime initialization of BRAM with MIF file - ( ‎04-08-2019 02:34 PM )

by on Latest post on by

3 Replies 925 Views

MicroBlaze design running in BRAM and DDR - ( ‎04-03-2019 02:38 PM )

by on Latest post on by

3 Replies 987 Views

Display image using VGA from BRAM - ( ‎02-19-2019 09:58 AM )

by on Latest post on by

11 Replies 3230 Views

How to correctly instantiate XPM memories so that ... - ( ‎01-27-2019 10:21 PM )

by on Latest post on by

2 Replies 1652 Views

BRAM initialization for Post-Synthesis simulation - ( ‎01-17-2019 07:40 AM )

by on

0 Replies 563 Views