Latest Tagged

Any examples of JESD PHY DRP configuration? - ( ‎01-22-2021 05:00 AM )

by on Latest post on by

1 Reply 133 Views

0

1

Virtex-6 GTX IP Sim. error - ( ‎11-22-2020 09:40 PM )

by on Latest post on by

1 Reply 278 Views

0

1

7-series GTX IBERT Example Design @ 0.625 Gbps - ( ‎11-16-2020 04:50 PM )

by on Latest post on by

1 Reply 269 Views

0

1

Kintex-7 10G-Ether PHY: About sharing coreclk and ... - ( ‎11-01-2020 11:08 PM )

by on Latest post on by

4 Replies 588 Views

0

4

Nonlinearity of eye scan function (Kintex-7 GTX t... - ( ‎07-14-2020 01:07 AM )

by on Latest post on by

5 Replies 663 Views

0

5

Dip in eye scan using DFE (Kintex-7 GTX transceive... - ( ‎06-26-2020 01:05 AM )

by on Latest post on by

4 Replies 789 Views

0

4

ALIGN primitive in 7series GTX as sata - ( ‎03-18-2020 06:25 AM )

by on Latest post on by

3 Replies 613 Views

0

3

Multi-lane GTX Transmitter Alignment - ( ‎02-27-2020 12:30 PM )

by on Latest post on by

1 Reply 522 Views

0

1

Error in SD-SDI transmission using GTX - ( ‎02-18-2020 06:22 AM )

by on Latest post on by

1 Reply 535 Views

0

1

Instantiating the IBERT 7 series GTX IP core - ( ‎02-07-2020 09:50 AM )

by on Latest post on by

2 Replies 570 Views

0

2

7 Series GTX - ( ‎11-11-2019 02:11 PM )

by on Latest post on by

1 Reply 403 Views

0

1

GTX CPLL occasionally not locking on powerup - ( ‎10-18-2019 10:39 AM )

by on Latest post on by

8 Replies 793 Views

0

8

MUXing 4:1 GTX clock unroutable placement - ( ‎09-04-2019 11:47 PM )

by on Latest post on by

2 Replies 637 Views

0

2

Scrambled data on GTX - ( ‎08-07-2019 02:14 AM )

by on Latest post on by

14 Replies 1062 Views

0

14

About COMMA detect in Virtex6 GTX - ( ‎05-14-2019 09:28 PM )

by on Latest post on by

2 Replies 523 Views

0

2

GTX transceiver in Kintex Ultrascale - ( ‎04-30-2019 03:02 PM )

by on Latest post on by

1 Reply 584 Views

0

1

ZC706 GT Serial TxRx - ( ‎04-25-2019 10:31 AM )

by on Latest post on by

2 Replies 621 Views

0

2

GTX, GTY far-end PCS - ( ‎03-27-2019 01:15 AM )

by on Latest post on by

1 Reply 562 Views

0

1

Aurora 64b66b MMCM and GTX locking - ( ‎12-04-2018 02:13 AM )

by on Latest post on by

4 Replies 1355 Views

0

4

7 Series GTX minimum line rate workaround - ( ‎10-17-2018 10:56 AM )

by on Latest post on by

4 Replies 1732 Views

0

4

Re: Preventing Vivado Synthesis removing un-driven... - ( ‎10-08-2018 02:49 AM )

by on

0 Replies 1737 Views

0

0

How to configure a GTX to support 10.0, 5.0, 2.5 ... - ( ‎08-23-2018 09:11 AM )

by on Latest post on by

12 Replies 2075 Views

0

12

RapidIO at 3.125Gbps can't link smoothly between X... - ( ‎07-16-2018 12:04 AM )

by on Latest post on by

1 Reply 858 Views

0

1

Configuring 7 series FPGA Transceiver wizard for V... - ( ‎06-13-2018 06:35 AM )

by on Latest post on by

6 Replies 2055 Views

0

6

Re: Virtex7 GTX transcievers wouldn't lock - ( ‎05-04-2018 10:10 AM )

by on

0 Replies 1836 Views

1

0

[7 Series GTX] RXUSRCLK2, RXUSRCLK, and RXOUTCLK t... - ( ‎03-13-2018 05:49 AM )

by on Latest post on by

5 Replies 1810 Views

0

5

GTX TX buffer bypass and multiple channels - ( ‎02-13-2018 11:46 AM )

by on Latest post on by

2 Replies 1658 Views

0

2

Eyescan CSV Header has invalid format [Labtools 27... - ( ‎02-05-2018 07:37 AM )

by on Latest post on by

3 Replies 1852 Views

0

3

Two CPRI cores in the same GTX? xc7z030ffg676-2 - ( ‎01-09-2018 01:59 AM )

by on Latest post on by

4 Replies 1610 Views

0

4

What does 'biased' mean for MGTXRXP/N pin on Table... - ( ‎11-27-2017 10:43 PM )

by on Latest post on by

5 Replies 2167 Views

0

5

Info: jitter integration bandwidth when using GTX/... - ( ‎09-22-2017 02:40 AM )

by on Latest post on by

2 Replies 1483 Views

0

2

GTX Transceiver CPLLFBCLKLOST - ( ‎07-27-2017 03:25 AM )

by on Latest post on by

3 Replies 3330 Views

0

3

jesd 204 channel bonding - ( ‎06-12-2017 06:09 AM )

by on Latest post on by

1 Reply 2958 Views

0

1

Setting GTX Attributes with IBERT - ( ‎06-09-2017 08:26 AM )

by on Latest post on by

1 Reply 2055 Views

0

1

7 series GTX : Disable Rx EQ - ( ‎05-31-2017 02:11 AM )

by on

0 Replies 2361 Views

0

0

GTX IO standards - ( ‎04-06-2017 06:49 AM )

by on Latest post on by

2 Replies 3603 Views

0

2

Aurora 8b10b only receiving sequence 0x4a4a - ( ‎03-02-2017 03:30 AM )

by on Latest post on by

5 Replies 4367 Views

0

5

GTX Transceiver design not working with latest too... - ( ‎12-16-2016 01:33 PM )

by on Latest post on by

12 Replies 5819 Views

0

12

Virtex-7 GTX: Feeding REFCLK from another RX chann... - ( ‎11-02-2016 09:21 AM )

by on Latest post on by

7 Replies 6521 Views

0

7

How do I enable the PCS functionality of GTX - 7 s... - ( ‎09-19-2016 10:53 PM )

by on Latest post on by

5 Replies 4161 Views

0

5

7Series Transceiver GTX Pattern checker - ( ‎09-05-2016 04:36 AM )

by on Latest post on by

8 Replies 7808 Views

0

8

IBERT 7 series issue - ( ‎08-24-2016 12:34 AM )

by on Latest post on by

9 Replies 8185 Views

0

9

CDR of 7 Series GTX - ( ‎08-15-2016 09:12 PM )

by on Latest post on by

16 Replies 9346 Views

0

16

7 Series GTX QPLL doubts - ( ‎08-10-2016 03:23 AM )

by on Latest post on by

17 Replies 9588 Views

0

17

Tuning of GTX Receiver for Custom Protocol - ( ‎08-04-2016 01:10 AM )

by on Latest post on by

9 Replies 8922 Views

0

9

Question About Unused GTX Pins - ( ‎07-14-2016 12:26 PM )

by on Latest post on by

1 Reply 5363 Views

0

1

When to schedule DRP operation - ( ‎07-14-2016 03:40 AM )

by on Latest post on by

1 Reply 4331 Views

0

1

RATE change in GTX zynq-706 - ( ‎07-12-2016 09:56 PM )

by on Latest post on by

9 Replies 5105 Views

0

9

GTX clock robustness lost after 2013.3 to 2015.4 V... - ( ‎05-25-2016 08:37 PM )

by on Latest post on by

4 Replies 7184 Views

0

4

DisplayPort sink with SSC on a kintex-7 FPGA. - ( ‎02-09-2016 09:04 AM )

by on Latest post on by

3 Replies 11026 Views

0

3