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Tag: " AXI Master"

Latest Tagged

Subject	Replies	Author	Kudos	Latest Post
Re: Implemented two different IPs using 32 and 64 ... - ( ‎02-03-2017 05:04 AM ) Embedded Processor System Design	2	cerilet	0	‎02-06-2017 09:01 AM by cerilet
Implemented two different IPs using 32 and 64 AXI ... - ( ‎02-01-2017 10:23 AM ) Embedded Processor System Design	4	cerilet	0	‎02-06-2017 09:01 AM by cerilet
I am not being able to write into DDR or OCM using... - ( ‎12-26-2016 12:13 PM ) Embedded Processor System Design	3	cerilet	0	‎12-27-2016 08:11 AM by muzaffer
Are these two block diagrams correct and have diff... - ( ‎12-19-2016 06:42 AM ) Design Entry	2	cerilet	0	‎12-20-2016 01:19 AM by cerilet
Control AXI DMA from PL module - ( ‎10-14-2016 05:17 AM ) High-Level Synthesis (HLS)	2	koidis	0	‎10-25-2016 11:56 PM by koidis
Re: How to read ethernet register in ZC706 - ( ‎10-23-2014 12:30 AM ) Xilinx Boards and Kits	0	muzaffer	1	‎10-23-2014 12:30 AM by muzaffer
Re: Vivado: create a simple AXI4-Master IP core - ( ‎03-07-2013 10:42 AM ) High-Level Synthesis (HLS)	3	markzak	0	‎03-11-2017 04:52 PM by bulunhaimu

Top Tagged

Subject	Replies	Author	Kudos	Latest Post
Re: Implemented two different IPs using 32 and 64 ... - ( ‎02-03-2017 05:04 AM ) Embedded Processor System Design	2	cerilet	0	‎02-06-2017 09:01 AM by cerilet
Implemented two different IPs using 32 and 64 AXI ... - ( ‎02-01-2017 10:23 AM ) Embedded Processor System Design	4	cerilet	0	‎02-06-2017 09:01 AM by cerilet
I am not being able to write into DDR or OCM using... - ( ‎12-26-2016 12:13 PM ) Embedded Processor System Design	3	cerilet	0	‎12-27-2016 08:11 AM by muzaffer
Are these two block diagrams correct and have diff... - ( ‎12-19-2016 06:42 AM ) Design Entry	2	cerilet	0	‎12-20-2016 01:19 AM by cerilet
Control AXI DMA from PL module - ( ‎10-14-2016 05:17 AM ) High-Level Synthesis (HLS)	2	koidis	0	‎10-25-2016 11:56 PM by koidis
Re: How to read ethernet register in ZC706 - ( ‎10-23-2014 12:30 AM ) Xilinx Boards and Kits	0	muzaffer	1	‎10-23-2014 12:30 AM by muzaffer
Re: Vivado: create a simple AXI4-Master IP core - ( ‎03-07-2013 10:42 AM ) High-Level Synthesis (HLS)	3	markzak	0	‎03-11-2017 04:52 PM by bulunhaimu

Top Taggers

User	Tag Count
cerilet	4
muzaffer	2
koidis	1