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Tag: "verilog"

Latest Tagged

Subject	Replies	Author	Latest Post
Real Time Clock Implementation in FPGA - ( ‎05-31-2017 12:43 AM ) Welcome & Join	2	knowfish	‎06-05-2017 06:52 PM by knowfish
How to create an AXI4 Master from a Verilog code a... - ( ‎04-25-2017 04:44 PM ) Design Entry	4	barry91	‎04-26-2017 07:47 AM by baf2099
not able to attached verilog files in XPS- illegal... - ( ‎04-19-2017 01:03 AM ) Embedded Development Tools	0	mkjaswal	‎04-19-2017 01:03 AM by mkjaswal
Re: inout from block giving weird error in synthes... - ( ‎04-06-2017 07:01 AM ) Synthesis	3	petersk	‎04-13-2017 03:31 PM by brimdavis
parallel vs sequencial - ( ‎03-01-2017 07:19 AM ) General Technical Discussion	2	alexmiculescu	‎03-04-2017 04:14 AM by u4223374
Re: "Default" values and case statements in Verilo... - ( ‎02-21-2017 10:07 PM ) Synthesis	5	evgenis1	‎02-22-2017 03:24 PM by zwabbit
Vivado15.2)Floating point in verilog - ( ‎02-13-2017 07:40 AM ) Simulation and Verification	2	grimlk	‎02-13-2017 09:09 AM by gszakacs
Synthesis based on different languages - ( ‎01-20-2017 05:35 PM ) Synthesis	5	bcura	‎01-29-2017 03:15 AM by anusheel
How to write a variable case statements in verilog - ( ‎01-12-2017 08:58 PM ) Design Methodologies and Advanced Tools	7	vinay1438	‎01-13-2017 06:22 AM by gszakacs
data path slack across multiple clock domains [ZYN... - ( ‎01-11-2017 10:13 AM ) Timing Analysis	9	sseppala	‎01-16-2017 06:47 AM by sseppala

Top Tagged

Subject	Replies	Author	Latest Post
Real Time Clock Implementation in FPGA - ( ‎05-31-2017 12:43 AM ) Welcome & Join	2	knowfish	‎06-05-2017 06:52 PM by knowfish
How to create an AXI4 Master from a Verilog code a... - ( ‎04-25-2017 04:44 PM ) Design Entry	4	barry91	‎04-26-2017 07:47 AM by baf2099
not able to attached verilog files in XPS- illegal... - ( ‎04-19-2017 01:03 AM ) Embedded Development Tools	0	mkjaswal	‎04-19-2017 01:03 AM by mkjaswal
Re: inout from block giving weird error in synthes... - ( ‎04-06-2017 07:01 AM ) Synthesis	3	petersk	‎04-13-2017 03:31 PM by brimdavis
parallel vs sequencial - ( ‎03-01-2017 07:19 AM ) General Technical Discussion	2	alexmiculescu	‎03-04-2017 04:14 AM by u4223374
Re: "Default" values and case statements in Verilo... - ( ‎02-21-2017 10:07 PM ) Synthesis	5	evgenis1	‎02-22-2017 03:24 PM by zwabbit
Vivado15.2)Floating point in verilog - ( ‎02-13-2017 07:40 AM ) Simulation and Verification	2	grimlk	‎02-13-2017 09:09 AM by gszakacs
Synthesis based on different languages - ( ‎01-20-2017 05:35 PM ) Synthesis	5	bcura	‎01-29-2017 03:15 AM by anusheel
How to write a variable case statements in verilog - ( ‎01-12-2017 08:58 PM ) Design Methodologies and Advanced Tools	7	vinay1438	‎01-13-2017 06:22 AM by gszakacs
data path slack across multiple clock domains [ZYN... - ( ‎01-11-2017 10:13 AM ) Timing Analysis	9	sseppala	‎01-16-2017 06:47 AM by sseppala

Top Taggers

User	Tag Count
gszakacs	18
zubin_kumar31	4
evgenis1	4
naikvihang	3
keithxilinx1	2