Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Account
My Account
Create Account
Sign Out
Search
All
Silicon Devices
Boards and Kits
Intellectual Property
Support
Documentation
Knowledge Base
Community Forums
Partners
Videos
Press
Search
Browse
Sign In
Help
petersk
Explorer
View all badges
Community Forums
:
About petersk
Latest posts by petersk
Subject
Views
Posted
Re: JESD204 relationship between sysref and refclk
Timing Analysis
2585
04-03-2018
06:57 AM
Re: JESD204 relationship between sysref and refclk
Timing Analysis
2607
04-02-2018
12:12 PM
Re: JESD204 relationship between sysref and refclk
Timing Analysis
2629
04-02-2018
07:19 AM
Re: JESD204 relationship between sysref and refclk
Timing Analysis
2675
03-30-2018
02:08 PM
Re: readmemh gives weird warning
Synthesis
1627
01-05-2018
06:55 AM
View All ≫
My Accepted Solutions
Subject
Views
Posted
Re: Match types between connected pins
Implementation
9093
05-24-2017
11:41 AM
Re: SSIN tied high for EMIO SPI bus
Processor System Design and AXI
6339
04-03-2017
08:04 PM
View All ≫
Community Statistics
Posts
154
Solutions
2
Kudos given
1
Kudos received
3
Member Since
07-29-2009
Contact Me
Online Status
Offline
Date Last Visited
05-30-2018
06:40 PM
Kudos from
Member
Kudos
lhjhit
1
avrumw
2
View All ≫
Kudos given to
Member
Kudos
ronnywebers
1
View All ≫
Latest Tags
JESD204B
SPI CLk
capture asynchronous
clock
Crash
SPI
xdc
EMIO
jesd
REFCLK
TIMING
$readmem
Absolute
axi lite
block design
btree
clocka
DDS
DIFF_TERM
DONT_TOUCH
Error
false path
File
GPIO
GTX Ref clk
import file
inout
JESD204
LCR
LVCMOS
View All ≫
