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petersk
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About petersk
Latest posts by petersk
Subject
Views
Posted
Re: JESD204 relationship between sysref and refclk
Timing Analysis
3055
04-03-2018
06:57 AM
Re: JESD204 relationship between sysref and refclk
Timing Analysis
3077
04-02-2018
12:12 PM
Re: JESD204 relationship between sysref and refclk
Timing Analysis
3099
04-02-2018
07:19 AM
Re: JESD204 relationship between sysref and refclk
Timing Analysis
3145
03-30-2018
02:08 PM
Re: readmemh gives weird warning
Synthesis
1982
01-05-2018
06:55 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Match types between connected pins
Implementation
9961
05-24-2017
11:41 AM
Re: SSIN tied high for EMIO SPI bus
Processor System Design and AXI
6720
04-03-2017
08:04 PM
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Community Statistics
Posts
154
Solutions
2
Kudos given
1
Kudos received
3
Member Since
07-29-2009
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Online Status
Offline
Date Last Visited
05-30-2018
06:40 PM
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avrumw
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ronnywebers
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Latest Tags
JESD204B
SPI CLk
capture asynchronous
clock
Crash
SPI
xdc
EMIO
jesd
REFCLK
TIMING
$readmem
Absolute
axi lite
block design
btree
clocka
DDS
DIFF_TERM
DONT_TOUCH
Error
false path
File
GPIO
GTX Ref clk
import file
inout
JESD204
LCR
LVCMOS
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