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abhinayp
Xilinx Employee
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About abhinayp
Latest posts by abhinayp
Subject
Views
Posted
How to handle more that 16 interrupts on a Versal ...
Design and Debug Techniques Blog
211
03-31-2021
08:27 PM
Re: ZU SD card problem
Processor System Design and AXI
67
03-25-2021
10:17 PM
Re: Zync ultascale+ Timer counter
Processor System Design and AXI
65
03-25-2021
10:15 PM
Re: 8 bit GPIO IP BLock
Processor System Design and AXI
81
03-25-2021
10:03 PM
Re: No reset_reason bit set by SWDT1 (FD4D0000)
ACAP and SoC Boot and Configuration
289
02-11-2021
12:01 PM
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My Accepted Solutions
Subject
Views
Posted
Re: More interrupts than normal required
Processor System Design and AXI
223
02-04-2021
08:51 AM
Re: tutorial for zcu102
Processor System Design and AXI
400
08-23-2020
08:27 AM
Re: Configuring external hardware interrupt to PS
Processor System Design and AXI
429
08-23-2020
08:02 AM
Re: Writing value on a pin on Zynq 7020
Processor System Design and AXI
429
07-19-2020
10:17 AM
Re: Floating point exception in microblaze process...
Processor System Design and AXI
456
07-19-2020
08:42 AM
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Community Statistics
Posts
141
Solutions
15
Kudos given
1
Kudos received
33
Member Since
07-12-2018
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Date Last Visited
03-31-2021
10:34 PM
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