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abhinayp
Xilinx Employee
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About abhinayp
Latest posts by abhinayp
Subject
Views
Posted
Re: Question about IRQ_F2P width in PS7
Processor System Design and AXI
120
05-17-2020
03:04 PM
Re: Send a signal from PS to PL
Processor System Design and AXI
82
05-17-2020
11:10 AM
Re: Question about IRQ_F2P width in PS7
Processor System Design and AXI
149
05-17-2020
11:02 AM
Re: RPU to PL IPI interrupt for Zynq Ultrascale
Processor System Design and AXI
57
05-17-2020
10:57 AM
Re: Data abort handler when accessing SD card
Processor System Design and AXI
56
05-17-2020
10:53 AM
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My Accepted Solutions
Subject
Views
Posted
Re: question about microblaze using XPS to add GPI...
Processor System Design and AXI
190
11-14-2019
12:34 AM
Re: Zynq SPI Communication
Processor System Design and AXI
344
04-12-2019
07:32 AM
Re: ( CAN in Zynq7000 using zc702 ) How to add and...
Processor System Design and AXI
400
03-17-2019
11:21 AM
Re: How to handle the IRQ and FIQ interrupts?
Processor System Design and AXI
638
02-24-2019
08:23 AM
Re: PL2PS Interrupts & HDF file
Processor System Design and AXI
484
02-17-2019
09:51 AM
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Community Stats
Posts
107
Solutions
9
Kudos Given
1
Kudos Received
20
Member Since
07-12-2018
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Date Last Visited
05-22-2020
03:44 PM
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