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deepwavebill
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About deepwavebill
Latest posts by deepwavebill
Subject
Views
Posted
Re: PCIe DMA H2C flow control
PCIe and CPM
209
02-25-2020
05:22 AM
Re: PCIe DMA H2C flow control
PCIe and CPM
249
02-24-2020
09:02 AM
PCIe DMA H2C flow control
PCIe and CPM
356
02-21-2020
06:11 AM
Re: Issues upgrading PCIe DMA core from 2017.4 to ...
PCIe and CPM
224
02-04-2020
01:09 PM
Re: AXI interconnect slaves hanging
Processor System Design and AXI
256
02-03-2020
08:16 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Programmable full flag incorrect reset value
Xilinx IP Catalog
1099
09-28-2018
07:03 AM
Re: JESD204 core IP example behavioral simulation
Simulation and Verification
1187
08-27-2018
04:32 PM
Re: PCIe DMA test bench combined with JESD204B IP ...
PCIe and CPM
847
08-21-2018
10:17 AM
Re: Formal port does not exist in entity
Simulation and Verification
1553
08-15-2018
06:50 AM
Re: Behavioral simulation analysis and compilation...
Simulation and Verification
1685
08-10-2018
08:05 AM
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Community Stats
Posts
46
Solutions
5
Kudos Given
10
Kudos Received
1
Member Since
08-09-2018
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Offline
Date Last Visited
02-25-2020
08:46 AM
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Latest Tags
accumulator
functional sim
JESD204 Core IP
JESD204 PHY core
mmcm
non-module files
Reset
sync reset
sysgen
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