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deepwavebill
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About deepwavebill
Latest posts by deepwavebill
Subject
Views
Posted
Re: MIG DDR4 write issues
Memory Interfaces and NoC
88
02-17-2021
04:38 PM
Re: MIG DDR4 write issues
Memory Interfaces and NoC
144
02-16-2021
02:11 PM
MIG DDR4 write issues
Memory Interfaces and NoC
224
02-15-2021
03:51 PM
Re: PCIe DMA H2C flow control
PCIe and CPM
462
02-25-2020
05:22 AM
Re: PCIe DMA H2C flow control
PCIe and CPM
502
02-24-2020
09:02 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Programmable full flag incorrect reset value
Xilinx IP Catalog
1353
09-28-2018
07:03 AM
Re: JESD204 core IP example behavioral simulation
Simulation and Verification
1414
08-27-2018
04:32 PM
Re: PCIe DMA test bench combined with JESD204B IP ...
PCIe and CPM
989
08-21-2018
10:17 AM
Re: Formal port does not exist in entity
Simulation and Verification
2026
08-15-2018
06:50 AM
Re: Behavioral simulation analysis and compilation...
Simulation and Verification
2028
08-10-2018
08:05 AM
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Community Statistics
Posts
49
Solutions
5
Kudos given
11
Kudos received
1
Member Since
08-09-2018
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Offline
Date Last Visited
02-17-2021
07:59 PM
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1
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Latest Tags
accumulator
functional sim
JESD204 Core IP
JESD204 PHY core
mmcm
non-module files
Reset
sync reset
sysgen
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