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deepwavebill
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About deepwavebill
Latest posts by deepwavebill
Subject
Views
Posted
回复： DDS compiler COS SIN LUT shortened output leng...
AI Engine, DSP IP and Tools
99
07-19-2021
07:04 AM
回复： DDS compiler COS SIN LUT shortened output leng...
AI Engine, DSP IP and Tools
170
07-16-2021
07:25 AM
回复： DDS compiler COS SIN LUT shortened output leng...
AI Engine, DSP IP and Tools
178
07-16-2021
06:41 AM
DDS compiler COS SIN LUT shortened output length
AI Engine, DSP IP and Tools
256
07-13-2021
07:31 AM
Re: System generator black box debug and memory us...
AI Engine, DSP IP and Tools
172
06-01-2021
06:38 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Programmable full flag incorrect reset value
Xilinx IP Catalog
1526
09-28-2018
07:03 AM
Re: JESD204 core IP example behavioral simulation
Simulation and Verification
1626
08-27-2018
04:32 PM
Re: PCIe DMA test bench combined with JESD204B IP ...
PCIe and CPM
1132
08-21-2018
10:17 AM
Re: Formal port does not exist in entity
Simulation and Verification
2411
08-15-2018
06:50 AM
Re: Behavioral simulation analysis and compilation...
Simulation and Verification
2259
08-10-2018
08:05 AM
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Community Statistics
Posts
75
Solutions
5
Kudos given
12
Kudos received
4
Member Since
08-09-2018
Contact Me
Online Status
Offline
Date Last Visited
07-19-2021
10:25 AM
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drjohnsmith
2
maps-mpls
1
venkata
1
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vkanchan
1
dgisselq
2
aforencich
1
xilinxacct
1
hemangd
1
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Latest Tags
accumulator
functional sim
JESD204 Core IP
JESD204 PHY core
mmcm
non-module files
Reset
sync reset
sysgen
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