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ezequielsasky
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About ezequielsasky
Latest posts by ezequielsasky
Subject
Views
Posted
Re: can't drive the cclk properly
FPGA Configuration
187
06-16-2021
10:12 AM
Re: GTP resets in example designgo nowhere
Serial Transceivers
288
06-16-2021
09:48 AM
Re: Selecting between two GTX REFCLKs (7 series)
Serial Transceivers
153
06-15-2021
03:32 PM
Selecting between two GTX REFCLKs (7 series)
Serial Transceivers
289
06-02-2021
04:33 PM
Re: [Place 30-410] clock placement error
Implementation
472
10-30-2020
11:09 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Selecting between two GTX REFCLKs (7 series)
Serial Transceivers
153
06-15-2021
03:32 PM
Re: Selecting one clock (RXUSRCLK) out of four GTX...
Implementation
725
10-06-2020
04:48 PM
Re: Differential clock driving one IBUFGDS and one...
Implementation
19243
12-17-2014
09:20 AM
Re: Unconnected blocks in VHDL code
General Technical Discussion
8829
12-05-2014
03:43 PM
Re: GT Transciever RX Data Valid signaling
Ethernet
15454
12-04-2014
12:10 PM
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Community Statistics
Posts
221
Solutions
27
Kudos given
8
Kudos received
27
Member Since
02-22-2010
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Date Last Visited
06-16-2021
01:53 PM
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