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kangsungsik
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About kangsungsik
Latest posts by kangsungsik
Subject
Views
Posted
Question about bitslip in 'High speed selectIO wiz...
Versal and UltraScale Architecture™
135
06-09-2020
12:45 AM
MMCM feedback clock frequency.
Versal and UltraScale Architecture™
153
06-03-2020
05:09 PM
Capturing ADC data UltraScale.
Versal and UltraScale Architecture™
155
05-27-2020
02:27 AM
Re: What does [byte group] mean in 'high speed sel...
Xilinx IP Catalog
274
05-20-2020
02:33 AM
Re: What does [byte group] mean in 'high speed sel...
Xilinx IP Catalog
295
05-20-2020
01:27 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Problem with selecting the version of FPGA dev...
Versal and UltraScale Architecture™
263
03-10-2020
01:46 AM
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Community Statistics
Posts
101
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1
Kudos given
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Kudos received
17
Member Since
11-20-2018
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Date Last Visited
06-16-2020
03:30 AM
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