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simon
Xilinx Employee
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About simon
Latest posts by simon
Subject
Views
Posted
回复: SnP Package Model file for Virtex Ultrascale+ ...
Versal and UltraScale Architecture™
67
04-08-2021
06:12 PM
回复: How to use IBERT with DMA/Bridge Subsystem for...
PCIe and CPM
160
04-06-2021
06:05 PM
回复: Good eye diagram but no link
Serial Transceivers
182
03-31-2021
06:08 PM
回复: GTP RX STARTUP FSM stuck at ASSERT ALL RESETS
Serial Transceivers
183
03-17-2021
06:17 PM
回复: FPGA加载技术
FPGA Configuration
93
03-03-2021
05:53 PM
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My Accepted Solutions
Subject
Views
Posted
回复: GTH scramber/descrambler polynomial
Serial Transceivers
205
02-24-2021
05:11 PM
回复: Virtex 5 - terminate unused differential I/O
FPGA Configuration
221
12-14-2020
07:46 PM
回复: Aurora IP Starting GT Quad Help
Xilinx IP Catalog
370
11-26-2020
12:53 AM
回复: Very low power analysis with a SAIF file
Vivado Debug and Power Estimation Tools
509
11-14-2020
01:33 AM
回复: Is it possible to program xc2c256 using vivado...
FPGA Configuration
391
09-09-2020
06:46 PM
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Community Statistics
Posts
874
Solutions
164
Kudos given
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Kudos received
280
Member Since
08-25-2010
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Date Last Visited
04-14-2021
03:39 AM
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