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josephsamson
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About josephsamson
Latest posts by josephsamson
Subject
Views
Posted
Master SPI Config Runs Forever With Blank Flash
FPGA Configuration
12
11-25-2020
01:53 PM
Re: Spartan 7 - Pin compatibility
Other FPGA Architecture
147
11-09-2020
05:15 AM
Re: IIC slave example - ReadBuffer problem
Processor System Design and AXI
196
09-01-2020
09:00 AM
Re: IIC slave example - ReadBuffer problem
Processor System Design and AXI
248
09-01-2020
04:45 AM
Re: Connecting Ethernet block to PHY on Zedboard
Ethernet
327
08-26-2020
05:07 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Connecting Ethernet block to PHY on Zedboard
Ethernet
411
08-25-2020
01:37 PM
Re: Restart Zynq From Watchdog
ACAP and SoC Boot and Configuration
447
05-21-2020
02:50 PM
Re: Interrupts Not Assigned in xparameters.h
Processor System Design and AXI
557
12-19-2019
05:13 AM
Re: DMA vs VDMA?
Video and Audio
460
12-09-2019
05:54 AM
Re: Can use a DDR3 as FIFO?
Memory Interfaces and NoC
853
01-21-2019
06:03 AM
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Community Statistics
Posts
234
Solutions
30
Kudos given
9
Kudos received
42
Member Since
10-05-2010
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Online
Date Last Visited
11-25-2020
11:44 AM
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arashr
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shengjie
1
savula
1
denist
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Latest Tags
ZYNQ
VDMA
AXI
DMA
FIFO
2019.2
axi stream
axi video stream
BRESP
chipscope
constraints
FIR filter
gmii_to_rgmii
GPIO
HSIZE
I2C
iic
ILA
ip repository
IRQ
LVDS
LVDS_25
MARK_DEBUG
microblaze
mig
MIG Artix-7
modport
modport systemverilog
pinout
PL
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