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josephsamson
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About josephsamson
Latest posts by josephsamson
Subject
Views
Posted
Re: **IMPORTANT** -- Kria Availability and Purchas...
Kria SOMs
200
07-12-2021
10:25 AM
Re: **IMPORTANT** -- Kria Availability and Purchas...
Kria SOMs
317
07-09-2021
05:28 AM
Re: **IMPORTANT** -- Kria Availability and Purchas...
Kria SOMs
378
07-08-2021
08:16 AM
Re: SystemVerilog function doesn't synthesis corre...
Synthesis
291
06-28-2021
01:49 PM
Re: Which VIVADO version can I use with ZYBO-Z7-10...
Other FPGA Architecture
100
06-24-2021
05:45 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Connecting Ethernet block to PHY on Zedboard
Ethernet
923
08-25-2020
01:37 PM
Re: Restart Zynq From Watchdog
ACAP and SoC Boot and Configuration
1307
05-21-2020
02:50 PM
Re: Interrupts Not Assigned in xparameters.h
Processor System Design and AXI
1214
12-19-2019
05:13 AM
Re: DMA vs VDMA?
Video and Audio
930
12-09-2019
05:54 AM
Re: Can use a DDR3 as FIFO?
Memory Interfaces and NoC
1154
01-21-2019
06:03 AM
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Community Statistics
Posts
259
Solutions
30
Kudos given
11
Kudos received
51
Member Since
10-05-2010
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Offline
Date Last Visited
07-12-2021
03:12 PM
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maps-mpls
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anatoli
2
m.torabi
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stephenm
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markg@prosensin
g.com
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Latest Tags
ZYNQ
VDMA
AXI
DMA
FIFO
2019.2
axi stream
axi video stream
BRESP
chipscope
constraints
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gmii_to_rgmii
GPIO
HSIZE
I2C
iic
ILA
ip repository
IRQ
LVDS
LVDS_25
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microblaze
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MIG Artix-7
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