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deepalir
Xilinx Employee
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About deepalir
Latest posts by deepalir
Subject
Views
Posted
回复： How to generate 32GB DDR4 core(SODIMM)?
Memory Interfaces and NoC
56
09-15-2020
04:03 PM
Re: How many DDR4 PHY can be instantiated in XCKU...
Memory Interfaces and NoC
248
08-12-2020
05:44 PM
Re: zynqmp_dram_test WrEye2D issue
Memory Interfaces and NoC
261
07-27-2020
09:09 AM
Re: connect custom ddr4 memory ZCU 104 PL side
Memory Interfaces and NoC
182
07-20-2020
10:15 AM
Re: ZCU104 Borad PL SODIMM RAM
Memory Interfaces and NoC
284
07-20-2020
09:56 AM
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My Accepted Solutions
Subject
Views
Posted
Re: zynqmp_dram_test WrEye2D issue
Memory Interfaces and NoC
261
07-27-2020
09:09 AM
Re: Configuration of the HBM controller of VCU128 ...
Memory Interfaces and NoC
470
06-24-2020
04:21 PM
Re: DDR4 clk to DQS Skew
Memory Interfaces and NoC
374
05-27-2020
12:48 PM
Re: Identification of failing byte on MIG DDR3
Memory Interfaces and NoC
346
03-16-2020
05:35 PM
Re: memory address for MIG in KC705
Memory Interfaces and NoC
430
01-28-2020
11:52 AM
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Community Statistics
Posts
37
Solutions
7
Kudos given
2
Kudos received
18
Member Since
02-21-2019
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Online Status
Offline
Date Last Visited
09-15-2020
07:25 PM
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calebd
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jie.zhang
1
kshimizu
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