Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Account
My Account
Create Account
Sign Out
Search
All
Silicon Devices
Boards and Kits
Intellectual Property
Support
Documentation
Knowledge Base
Community Forums
Partners
Videos
Press
Search
Browse
Sign In
Help
zubinkumar
Observer
View all badges
Community Forums
:
About zubinkumar
Latest posts by zubinkumar
Subject
Views
Posted
Re: reg: register to wire mapping in verilog
General Technical Discussion
23319
10-22-2013
09:18 AM
reg: register to wire mapping in verilog
General Technical Discussion
23330
10-22-2013
06:51 AM
Reg: Speeding up ISE 10.1 compilation time ... swi...
General Technical Discussion
5306
09-25-2013
12:07 PM
Reg: Speeding up ISE 10.1 compilation time ... swi...
Embedded Development Tools
2671
09-25-2013
11:44 AM
controlling hold time using offset out constraint ...
Timing Analysis
6941
11-16-2012
02:38 PM
View All ≫
My Accepted Solutions
Subject
Views
Posted
Re: FPGA design switching between 2 clock frequenc...
General Technical Discussion
24969
09-04-2012
12:37 PM
View All ≫
Community Statistics
Posts
33
Solutions
1
Kudos given
0
Kudos received
0
Member Since
11-23-2010
Contact Me
Online Status
Offline
Date Last Visited
10-22-2013
05:25 PM
Latest Tags
xilinx
10.1
ISE
ISE 10.1
speed up
12.1
Chipscope 10
compile time
floorplan
fpga
hold time
modelsim
OFFSET OUT
PCI
PlanAhead
post PAR
TIMING
XtremeDSP kit 4
board kit xtremeDSP kit…
clock
COREgen
dcm
delay
external clock
FD based shift register
frequency
frequency range
IP CORE
ise 10.1 ise 11.1 ise 1…
ISE 11.1
View All ≫
