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zubinkumar
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About zubinkumar
Latest posts by zubinkumar
Subject
Views
Posted
Re: reg: register to wire mapping in verilog
General Technical Discussion
24585
10-22-2013
09:18 AM
reg: register to wire mapping in verilog
General Technical Discussion
24596
10-22-2013
06:51 AM
Reg: Speeding up ISE 10.1 compilation time ... swi...
General Technical Discussion
5377
09-25-2013
12:07 PM
Reg: Speeding up ISE 10.1 compilation time ... swi...
Embedded Development Tools
2741
09-25-2013
11:44 AM
controlling hold time using offset out constraint ...
Timing Analysis
6975
11-16-2012
02:38 PM
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My Accepted Solutions
Subject
Views
Posted
Re: FPGA design switching between 2 clock frequenc...
General Technical Discussion
25327
09-04-2012
12:37 PM
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Community Statistics
Posts
33
Solutions
1
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0
Kudos received
0
Member Since
11-23-2010
Contact Me
Online Status
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Date Last Visited
10-22-2013
05:25 PM
Latest Tags
xilinx
10.1
ISE
ISE 10.1
speed up
12.1
Chipscope 10
compile time
floorplan
fpga
hold time
modelsim
OFFSET OUT
PCI
PlanAhead
post PAR
TIMING
XtremeDSP kit 4
board kit xtremeDSP kit…
clock
COREgen
dcm
delay
external clock
FD based shift register
frequency
frequency range
IP CORE
ise 10.1 ise 11.1 ise 1…
ISE 11.1
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