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kren
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About kren
Latest posts by kren
Subject
Views
Posted
回复: DDR MIG example_design Simulation: ERROR: Acti...
Memory Interfaces and NoC
73
04-09-2021
02:45 AM
回复: OSERDESE3 Skew Check: Implement for own realiz...
Versal and UltraScale Architecture™
138
04-09-2021
02:41 AM
回复: DDR4 (MIG) IP refresh rate and military temper...
Memory Interfaces and NoC
60
04-06-2021
02:35 AM
回复: Spartan 6 FPGA and DDR3 DRAM memory interface ...
Memory Interfaces and NoC
217
04-01-2021
02:06 AM
回复: Spartan 6 FPGA and DDR3 DRAM memory interface ...
Memory Interfaces and NoC
267
03-31-2021
02:43 AM
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My Accepted Solutions
Subject
Views
Posted
回复: Post-synthesis simulation with Xilinx PHY - Ca...
Memory Interfaces and NoC
293
03-31-2021
02:33 AM
回复: Does Cadence Xcelium support HBM simulation?
Memory Interfaces and NoC
214
03-23-2021
02:26 AM
回复: MPSoC PL DDR eye test
Memory Interfaces and NoC
177
02-24-2021
12:26 AM
回复: I get error when "pin selection" in MIG genera...
Memory Interfaces and NoC
198
02-04-2021
11:20 PM
回复: 64 bit DDR3 address/Control ports selection
Memory Interfaces and NoC
258
01-12-2021
07:29 PM
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Kudos received
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Member Since
08-21-2007
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04-14-2021
05:54 AM
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