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naz_rb
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About naz_rb
Latest posts by naz_rb
Subject
Views
Posted
Simple Dual Port URAM read and write simultaneousl...
Xilinx IP Catalog
327
05-16-2020
06:08 PM
ZYNQ writes only LSB byte to a 32bit register of a...
High-Level Synthesis (HLS)
374
04-04-2020
10:23 PM
Re: How to properly cast unsigned to signed
High-Level Synthesis (HLS)
423
03-18-2020
06:58 AM
Re: How to properly cast unsigned to signed
High-Level Synthesis (HLS)
434
03-18-2020
06:40 AM
How to properly cast unsigned to signed
High-Level Synthesis (HLS)
526
03-16-2020
05:36 PM
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My Accepted Solutions
Subject
Views
Posted
Re: Xilinx SDK drivers "ps" meaning
Processor System Design and AXI
342
03-05-2020
05:35 AM
Re: HLS 2019 is missing libpng12.so on LTS 18.04
High-Level Synthesis (HLS)
743
12-12-2019
06:16 AM
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Community Statistics
Posts
65
Solutions
2
Kudos given
25
Kudos received
2
Member Since
11-10-2019
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Offline
Date Last Visited
05-20-2020
10:48 AM
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jg_spitfire
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avrumw
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abouassi
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Latest Tags
HLS
BRAM
synthesis
utilization
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