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vsrunga
Xilinx Employee
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About vsrunga
Latest posts by vsrunga
Subject
Views
Posted
Re: SOM second connector pinout and 1_b16/1_c24 co...
Kria SOMs
134
07-30-2021
03:13 AM
Re: SOM second connector pinout and 1_b16/1_c24 co...
Kria SOMs
175
07-30-2021
12:07 AM
Re: SOM second connector pinout and 1_b16/1_c24 co...
Kria SOMs
240
07-29-2021
02:29 AM
Re: SOM second connector pinout and 1_b16/1_c24 co...
Kria SOMs
262
07-28-2021
10:28 PM
Re: Define a custom IP that connects with Board Co...
Design Entry
61
07-27-2021
09:46 PM
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My Accepted Solutions
Subject
Views
Posted
Re: SOM second connector pinout and 1_b16/1_c24 co...
Kria SOMs
175
07-30-2021
12:07 AM
Re: How to choose verilog code for packaging ip
Xilinx IP Catalog
60
07-26-2021
03:59 AM
Re: Unable to re-edit custom IP.
Processor System Design and AXI
231
07-15-2021
02:44 AM
Re: Board Inerface files
Vivado Debug and Power Estimation Tools
458
05-03-2021
09:48 PM
Re: HDL Parser errors in IP Packager
Design Entry
301
04-28-2021
12:06 AM
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Community Statistics
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4380
Solutions
901
Kudos given
308
Kudos received
613
Member Since
11-07-2011
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Date Last Visited
08-04-2021
06:56 AM
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