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vsrunga
Xilinx Employee
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About vsrunga
Latest posts by vsrunga
Subject
Views
Posted
Re: Change IP-Core Parameters in instantiation
Design Entry
82
02-15-2021
02:51 AM
Re: [BUG] Generated makefile of custom IP-Core not...
Design Entry
105
02-09-2021
07:16 AM
Re: [BUG] Edit-IP: simulation not working by defau...
Design Entry
108
02-09-2021
07:07 AM
Re: Adding RTL module to block design - Incompatib...
Design Entry
248
02-09-2021
06:28 AM
Re: [BUG] Edit-IP: simulation not working by defau...
Design Entry
137
02-09-2021
02:48 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Adding RTL module to block design - Incompatib...
Design Entry
248
02-09-2021
06:28 AM
Re: Vivado IP Packager - variable Port Size
Design Entry
120
02-04-2021
10:12 PM
Re: Custom IP creation error “ERROR: [Common 17-3...
Synthesis
750
07-15-2020
04:58 AM
Re: IP packaging and customization parameters mana...
Design Entry
810
06-24-2020
04:51 AM
Re: Schematics for VMK180 or VCK190
Xilinx Evaluation Boards
837
06-09-2020
10:15 PM
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Community Statistics
Posts
4329
Solutions
892
Kudos given
308
Kudos received
595
Member Since
11-07-2011
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Date Last Visited
02-15-2021
07:37 AM
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