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geoffbarnes
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About geoffbarnes
Latest posts by geoffbarnes
Subject
Views
Posted
Re: What's your opinion on the legality of this VH...
Synthesis
950
03-03-2019
11:36 AM
Re: Syntax error when using $fopen!
Vivado TCL Community
1603
04-20-2018
06:02 AM
Re: Falling edge Clocked code produces LUT on cloc...
Synthesis
2209
04-19-2018
04:45 AM
Re: Falling edge Clocked code produces LUT on cloc...
Synthesis
2261
04-18-2018
06:02 PM
Re: Conversion error between unsigned and natural
Synthesis
2044
04-09-2018
06:32 PM
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My Accepted Solutions
Subject
Views
Posted
Re: Syntax error when using $fopen!
Vivado TCL Community
1603
04-20-2018
06:02 AM
Re: Understanding how blocking and non blocking st...
Synthesis
1669
03-13-2018
07:07 PM
Re: [VHDL] 'others' for highest part of the vector
Design Methodologies and Advanced Tools
8173
12-08-2017
10:55 AM
Re: [VHDL] procedure -> can be concurrent assignme...
Design Methodologies and Advanced Tools
2548
11-26-2017
03:24 PM
Re: [VHDL] packages -> super-package -> how-to?
Design Methodologies and Advanced Tools
2057
11-26-2017
02:22 PM
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Community Statistics
Posts
249
Solutions
25
Kudos given
13
Kudos received
78
Member Since
09-07-2011
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