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Latest posts by geoffbarnes

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Posted

Re: What's your opinion on the legality of this VH...

424

‎03-03-2019 11:36 AM

Re: Syntax error when using $fopen!

1168

‎04-20-2018 06:02 AM

Re: Falling edge Clocked code produces LUT on cloc...

1461

‎04-19-2018 04:45 AM

Re: Falling edge Clocked code produces LUT on cloc...

1513

‎04-18-2018 06:02 PM

Re: Conversion error between unsigned and natural

1298

‎04-09-2018 06:32 PM

My Accepted Solutions

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Posted

Re: Syntax error when using $fopen!

1168

‎04-20-2018 06:02 AM

Re: Understanding how blocking and non blocking st...

1199

‎03-13-2018 07:07 PM

Re: [VHDL] 'others' for highest part of the vector

3136

‎12-08-2017 10:55 AM

Re: [VHDL] procedure -> can be concurrent assignme...

2068

‎11-26-2017 03:24 PM

Re: [VHDL] packages -> super-package -> how-to?

1746

‎11-26-2017 02:22 PM

Community Stats

Posts	249
Solutions	25
Kudos Given	13
Kudos Received	78
Member Since	‎09-07-2011

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