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leonardooalves
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About leonardooalves
Latest posts by leonardooalves
Subject
Views
Posted
Undefined C timing system task and reg
Simulation and Verification
31
01-20-2021
04:45 AM
Re: JTAG for a custom processor
Processor System Design and AXI
208
12-07-2020
05:42 AM
JTAG for a custom processor
Processor System Design and AXI
283
12-04-2020
02:59 PM
Re: Connect and synthesize multiple top-modules
Synthesis
283
11-26-2020
03:15 AM
Re: Connect and synthesize multiple top-modules
Synthesis
318
11-25-2020
03:57 PM
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Member Since
11-24-2020
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Date Last Visited
01-20-2021
08:07 AM
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Latest Tags
verilog
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block design
C
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custom processor
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ip cores
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