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sraza
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About sraza
Latest posts by sraza
Subject
Views
Posted
difference between three NCD files
Implementation
7269
03-22-2014
08:59 AM
Re: DDR3 BL8 query, regarding data values and DDR3...
Memory Interfaces and NoC
8040
02-27-2014
03:05 AM
info about used logic analyzer compatible for chip...
Vivado Debug and Power Estimation Tools
7622
01-01-2014
05:35 AM
Re: Is there a way to detect a signal combination ...
Vivado Debug and Power Estimation Tools
16963
12-17-2013
11:47 PM
Re: partial data corruption while DDR3 read.
Memory Interfaces and NoC
10664
12-17-2013
11:39 PM
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My Accepted Solutions
Subject
Views
Posted
Re: Is there a way to detect a signal combination ...
Vivado Debug and Power Estimation Tools
16963
12-17-2013
11:47 PM
Re: Can we give continuous write/read (APP_ADDR / ...
Memory Interfaces and NoC
15796
12-17-2013
11:18 PM
Re: data shifting for writing INTO DDR3 using MIG
Memory Interfaces and NoC
13917
12-02-2013
10:10 PM
Re: debugging MIG based desing for DDR3 communicat...
Memory Interfaces and NoC
11669
11-24-2013
04:54 AM
Re: partial data corruption while DDR3 read.
Memory Interfaces and NoC
17284
11-22-2013
06:54 AM
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Community Statistics
Posts
172
Solutions
10
Kudos given
18
Kudos received
2
Member Since
03-13-2012
Contact Me
Online Status
Offline
Date Last Visited
03-22-2014
12:36 PM
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vsrunga
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eteam00
1
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vsrunga
6
gszakacs
1
vemulad
1
sauravs
1
muzaffer
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Latest Tags
chipscope
4dsp
BPI PROM configuration
logic analyzer
stellar IP
2 compliment divider
4dsp. PCIe programming
ADC and FIFO interfacin…
app_rdy LOW
AUTORESET_PATDET
BL8
burst length DDR3
burst read
Chipscope PCIe
Configuration problem
Connection to ground
consecutive_read_write
constellation
custom DDR3 part
Custom MIG design
DDR3 adrresing
DDR3 clock
DDR3 column
DDR3 data corruption
DDR3 debugging
debug PCIe design
default address width
dowlaod modelsim
fft
fft sine wave
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