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richardhead
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About richardhead
Latest posts by richardhead
Subject
Views
Posted
Re: Use " array" in VHDL
Synthesis
86
04-19-2021
03:50 AM
Re: Use " array" in VHDL
Synthesis
125
04-19-2021
02:42 AM
Re: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_...
Simulation and Verification
148
04-16-2021
02:53 PM
Re: Suppress RTL Hierarchical Component Statistics
Embedded Development Tools
85
04-15-2021
03:13 PM
Re: 4-bit ALU having syntax and other errors, advi...
Synthesis
116
04-15-2021
01:21 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Vulnerability analysis on FPGA code
Other FPGA Architecture
117
04-14-2021
01:11 AM
回复： UltraScale+ 100G MAC AXIS strange behaviour un...
Ethernet
117
04-12-2021
03:32 PM
Re: Different bitsream is generated when I create ...
Implementation
196
04-05-2021
02:53 AM
Re: One or two process state machines, does it aff...
Synthesis
234
04-04-2021
03:38 PM
Re: Transition from modelsim to vivado sim
Simulation and Verification
228
03-24-2021
01:09 AM
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Community Statistics
Posts
1691
Solutions
189
Kudos given
95
Kudos received
889
Member Since
08-01-2012
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Date Last Visited
04-19-2021
03:48 AM
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