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shantmoses
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About shantmoses
Latest posts by shantmoses
Subject
Views
Posted
Re: VHDL Generate Statement
Synthesis
506
07-03-2021
01:27 PM
Re: VHDL Generate Statement
Synthesis
509
07-03-2021
01:16 PM
Re: Changing the si5341 clock frequency on the ZCU...
Embedded Linux
191
06-19-2021
12:30 PM
RFSoC multi-tile sync clock rates
Versal and UltraScale Architecture™
444
06-02-2021
05:13 PM
Re: Zynq UltraScale+ PS_ERROR_OUT Custom Board
ACAP and SoC Boot and Configuration
484
05-07-2021
10:06 AM
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My Accepted Solutions
Subject
Views
Posted
Re: ZCU208 - Discrepancy between latest board sche...
Implementation
1019
12-25-2020
10:02 PM
Re: Simple VHDL code, can't simulate because of a ...
Simulation and Verification
546
12-16-2020
05:19 PM
Re: mixing verilog code with vhdl declaration issu...
Design Entry
374
10-05-2020
04:50 PM
Re: Spartan-6 LX25T BUFIO2 clocking regions
Implementation
16460
07-25-2014
04:43 PM
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Community Statistics
Posts
51
Solutions
5
Kudos given
18
Kudos received
19
Member Since
07-01-2008
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Date Last Visited
07-03-2021
04:48 PM
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patocarr
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denist
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banality
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