About danpianji88 - Community Forums

UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Explorer

Latest posts by danpianji88

Subject

Views

Posted

How to reduce the delay of two output signal?

216

‎12-18-2018 06:59 AM

回复： GTP: 8B/10B encoding

298

‎10-25-2018 08:41 PM

回复： GTP: 8B/10B encoding

327

‎10-24-2018 08:09 PM

回复： GTP: 8B/10B encoding

375

‎10-21-2018 07:55 PM

回复： About aurora 8b/10b back channel of timer

224

‎10-21-2018 06:49 PM

My Accepted Solutions

Subject

Views

Posted

Re: about vdma v6.2

912

‎03-21-2018 06:00 PM

Re: About axi-stream interconnect v2.1

7311

‎02-09-2017 04:11 AM

Re: Module in debussy is unknown

8685

‎12-11-2013 05:43 PM

Re: how to use burst operation with axi4 bus

5994

‎12-10-2013 01:15 AM

Community Stats

Posts	131
Solutions	4
Kudos Given	0
Kudos Received	0
Member Since	‎01-04-2013