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jg_bds
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About jg_bds
Latest posts by jg_bds
Subject
Views
Posted
Re: Configuration flash programming fails if the A...
FPGA Configuration
4083
10-23-2020
06:55 AM
Re: Configuration flash programming fails if the A...
FPGA Configuration
4098
10-23-2020
06:20 AM
Re: SDIO EMIO for MPSoC
Processor System Design and AXI
924
07-28-2020
12:48 PM
Re: SDIO EMIO for MPSoC
Processor System Design and AXI
933
07-28-2020
12:22 PM
Re: SDIO EMIO for MPSoC
Processor System Design and AXI
956
07-28-2020
07:44 AM
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My Accepted Solutions
Subject
Views
Posted
Re: LPDDR4 routing-skew requirement deratings for ...
Memory Interfaces and NoC
572
11-05-2019
08:25 AM
Re: Unspecified I/O standard in AXI GPIO when set ...
Processor System Design and AXI
966
10-14-2019
01:44 PM
Re: more than 64 emio pins of zynq ?
Processor System Design and AXI
641
10-14-2019
12:38 PM
Re: How to make a pin to be Differential LVDS?
Design Entry
2072
09-21-2019
07:43 PM
Re: Is it necessary to assign port Type to a i/o p...
Design Entry
696
09-21-2019
07:19 PM
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Community Statistics
Posts
620
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Member Since
02-01-2013
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Date Last Visited
10-23-2020
11:21 AM
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7 Series
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