All
Silicon Devices
Boards and Kits
Intellectual Property
Support
Documentation
Knowledge Base
Community Forums
Partners
Videos
Press
Applications
Products
Developers
Support
About
Account
My Account
Create Account
Sign Out
Search
All
Silicon Devices
Boards and Kits
Intellectual Property
Support
Documentation
Knowledge Base
Community Forums
Partners
Videos
Press
Search
Browse
Sign In
Help
nathanx
Moderator
View all badges
Community Forums
:
About nathanx
Latest posts by nathanx
Subject
Views
Posted
回复： SD-FEC issue in 5G LDPC encode mode (Vivado 20...
Xilinx IP Catalog
66
05-18-2020
02:16 AM
回复： xfix numbers
AI Engine, DSP IP and Tools
59
05-18-2020
02:14 AM
回复： FFT IP Core performance limit for RFSoC
AI Engine, DSP IP and Tools
103
05-18-2020
02:10 AM
回复： DSP48E2 Subtraction output wrong
AI Engine, DSP IP and Tools
68
05-11-2020
09:43 PM
回复： Up/down Mixer transceiver
AI Engine, DSP IP and Tools
61
05-11-2020
09:41 PM
View All ≫
My Accepted Solutions
Subject
Views
Posted
回复： Maximum coefficeint sets for FIR compiler 7.2:...
Xilinx IP Catalog
255
02-07-2020
07:09 PM
回复： JESD core to transmit 2 IQ signals.
Xilinx IP Catalog
203
01-21-2020
10:24 PM
回复： why does vivado infer 25bit x 18bit mutiplier ...
Synthesis
257
01-01-2020
06:15 PM
回复： Xilinx DUC/DDC for 5G NR
Xilinx IP Catalog
273
12-26-2019
06:59 PM
回复： JESD IP CORE not working
Xilinx IP Catalog
360
12-08-2019
11:53 PM
View All ≫
Community Stats
Posts
825
Solutions
102
Kudos Given
2
Kudos Received
133
Member Since
08-01-2007
Contact Me
Online Status
Offline
Date Last Visited
05-18-2020
05:39 AM
Kudos from
Member
Kudos
hiroaki4625
1
karnanl
4
joe306
1
mirzamihsanbaig
1
yuko.2828
1
View All ≫
Kudos given to
Member
Kudos
meherp
1
View All ≫
Latest Tags
OK
pP
两种可能性:
View All ≫
