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	DMA by motagiyash Observer in AXI Infrastructure 04-24-2019 0 1	0	1
	zynq以太网找不到phy by quake Visitor in 嵌入式软件开发 04-24-2019 0 4	0	4
	ZCU-102 Bare Metal JTAG Debug by ilya.kochub Visitor in Embedded Boot and Configuration 04-24-2019 0 7	0	7
	GTH 数据传输 by sdersder Observer in 7 Series FPGA & 其他 FPGA 器件 04-24-2019 0 3	0	3
	Ubuntu Desktop and Generic UIO by rashedkoutayni Contributor in Embedded Linux 04-24-2019 0 9	0	9
	MMCM DRP by whelm Explorer in Other FPGA Architectures 04-24-2019 0 1	0	1
	Video: Simple video masking doesn't work by kodukulav Adventurer in Vivado High-Level Synthesis (HLS) 04-24-2019 0 7	0	7
	Vivado crashes in batch mode, but not when using the GUI by xilinx@ober-mail.de Visitor in Design Entry 04-24-2019 0 6	0	6
	请问有没有人在sdx中使用xfft，能否提供一下sdx中使用xfft的文档资料，我找不到这个 by mu_yu Visitor in SDx 04-24-2019 0 3	0	3
	Does Vivado 2016.4 support VHDL-2008 Alias? by app076 Visitor in Simulation and Verification 04-24-2019 0 2	0	2
	ISE 14.7 impact error message 2862 by mcurtis Newbie in Configuration 04-24-2019 0 4	0	4
	question on parallelizing arithmetic operations by mahesh.barve@tcs.com Adventurer in Vivado High-Level Synthesis (HLS) 04-24-2019 0 1	0	1
	ADAS Front Camera with Xilinx-powered AI has entered mass production at BYD by gregmart Xilinx Employee in AI and Machine Learning Blog 04-24-2019 0 0	0	0
	Vivado 2017.3 VHDL-2008, Array of std_logic_vector not assigned correctly by nikhenri Observer in Synthesis 04-24-2019 0 1	0	1
	Vivado 2017.3 VHDL-2008, Array of Array of std_logic_vector syntax error generate EXCEPTION_ACCESS_VIOLATION by nikhenri Observer in Synthesis 04-24-2019 0 1	0	1
	awkward result in post implementation timing simulation by fpgatr Contributor in Simulation and Verification 04-24-2019 0 2	0	2
	xlopencv, api for void matchTemplate(InputArray image, InputArray templ, OutputArray result, int method)¶ by vlakhani Newbie in Open Source and Community Projects Discussion 04-24-2019 0 0	0	0
	How to map the AXI4 address to the ddr4 memory address? by johnmaclellan Participant in Memory Interfaces 04-24-2019 0 2	0	2
	No tftp server found by beenish.khan Visitor in Embedded Linux 04-24-2019 0 0	0	0
	Is it usual that an application runs faster in PetaLinux than in baremetal application? by tiago0297 Adventurer in Embedded Processor System Design 04-24-2019 0 0	0	0
	LVDS pins before configuration by john Visitor in Other FPGA Architectures 04-24-2019 0 8	0	8
	Zynq-7000 Interrupt management - Problem by ric.carbone@studenti.unina.it Visitor in Embedded Processor System Design 04-24-2019 0 4	0	4
	Xilskey Library in PetaLinux 2018.3 to Access PS DNA registers by tscbailey Observer in Embedded Linux 04-24-2019 0 1	0	1
	OpenAMP polling mode only?? by simon.beaudoin Observer in OpenAMP 04-24-2019 0 1	0	1
	RPMsg Zero-Copy Send and Receive Usage by jrp Adventurer in OpenAMP 04-24-2019 0 1	0	1
	How to change the rpmsg buffer size by waming@zhen Visitor in OpenAMP 04-24-2019 0 1	0	1
	QSPI (dual quad) under Petalinux 2018.3 not detecting by bfrazier_arete Adventurer in Embedded Linux 04-24-2019 0 3	0	3
	Artix7 Package/Speed combination does not exist in Vivado? by jwu1 Visitor in Other FPGA Architectures 04-24-2019 0 3	0	3
	[Petalinux 2018.2] build sdk fails, not enough space on 1TB SSD (~460GB still free) by freddy1404 Newbie in Embedded Linux 04-24-2019 0 1	0	1
	How to get a low clocking rate by ARTY 7 ? by ahmed_alfadhel Adventurer in Other FPGA Architectures 04-24-2019 0 0	0	0
	Artix-7 devices failing - power rails shorted to GND by tscarsbrook Visitor in Other FPGA Architectures 04-24-2019 0 4	0	4
	The application was unable to start correctly(0xc0000142). by mallika@1 Newbie in Configuration 04-24-2019 0 2	0	2
	Problem running app on embedded linux by elliottal Participant in Embedded Linux 04-24-2019 0 0	0	0
	lack of support for to-string by jkirby Visitor in Simulation and Verification 04-24-2019 0 7	0	7
	7 Series FPGAs Integrated Block for PCI Express v3.3 on CMOD-A7-35T board by charleslili Visitor in PCI Express 04-24-2019 0 2	0	2
	AXI blocks work at different clock frequencies by harish-anil Observer in Embedded Linux 04-24-2019 0 1	0	1
	Retiming in Vivado Synthesis by carmelo16 Newbie in Synthesis 04-24-2019 0 3	0	3
	Cortex-A9 IRQ with priority over configMAX_API_CALL_INTERRUPT_PRIORITY / Motor Control by @bucky Observer in Embedded Processor System Design 04-24-2019 0 1	0	1
	De-interlacer Quality by kevin.coombs@ge.com Visitor in Video 04-24-2019 0 0	0	0
	Process cannot have both a wait statement and a sensitivity list by siva407123_lak Visitor in Open Source and Community Projects Discussion 04-24-2019 0 2	0	2
	please help to improve DDR configuration by hyphen Visitor in Embedded Processor System Design 04-24-2019 0 0	0	0
	Supported Flash Devices by bhall0107 Observer in Embedded Boot and Configuration 04-24-2019 0 0	0	0
	Vivado download problems (The file you have requested is not available) by awais9800 Visitor in Installation and Licensing 04-24-2019 0 3	0	3
	RFSOC LVM Data format and file size by arve9066 Visitor in UltraScale Architecture™ 04-24-2019 0 2	0	2
	IBIS MODEL FOR XQ7Z030-1RB484Q (Zynq-7000Q) by abhilash.p Visitor in Other FPGA Architectures 04-24-2019 0 2	0	2
	Programming Si570 on custom board by trinadhkosuru Observer in UltraScale Architecture™ 04-24-2019 0 0	0	0
	Removing Packages does not decrease image size (Petalinux) by eliezer Visitor in Embedded Linux 04-24-2019 0 0	0	0
	float and ap_uint issue by mahesh.barve@tcs.com Adventurer in Vivado High-Level Synthesis (HLS) 04-24-2019 0 7	0	7
	Use PL as Userspace IO Device by rashedkoutayni Contributor in Embedded Linux 04-24-2019 0 23	0	23
	Implementing FMC HPC on KC705 by erdewey@ncsu.edu Visitor in Evaluation Boards 04-24-2019 0 1	0	1
	Varying error behaviour on post synthesis simulation by eldercosta Adventurer in Simulation and Verification 04-24-2019 0 1	0	1
	rfdc configuration on linux by cesanka Adventurer in OpenAMP 04-24-2019 0 1	0	1
	Zynq-7000 Configure PPI IRQ with Kernel Module by ryandunn19 Observer in Embedded Processor System Design 04-24-2019 0 0	0	0
	Virtex-5 Allowable Downward Pressure by petrivka Newbie in Other FPGA Architectures 04-24-2019 0 0	0	0
	FFT core v7.1 for Virtex 4 device MATLAB model by ubhatia7 Visitor in DSP IP and Tools 04-24-2019 0 3	0	3
	testing purpose by dewd551@gmail.com Visitor in Open Source and Community Projects Discussion 04-24-2019 0 1	0	1
	CMOD xc7s25 XADC by joshnatalina Newbie in Other FPGA Architectures 04-24-2019 0 1	0	1
	SPI Loopback by zuzu@123 Observer in UltraScale Architecture™ 04-24-2019 0 0	0	0
	lwIP KeepAlive by greengoose Visitor in Other FPGA Architectures 04-24-2019 0 0	0	0
	Unexpected error while launching program: Error while running ps7_init method. Cannot write to target Cannot access JTAG-DP: invalid ACK value (0x00, expected=0x02) Error Address = 0xf8000778 by nagavenkat@ecsonweb.com Visitor in Embedded Processor System Design 04-24-2019 0 2	0	2