All
Silicon Devices
Boards and Kits
Intellectual Property
Support
Documentation
Knowledge Base
Community Forums
Partners
Videos
Press
Applications
Products
Developers
Support
About
Account
My Account
Create Account
Sign Out
Search
All
Silicon Devices
Boards and Kits
Intellectual Property
Support
Documentation
Knowledge Base
Community Forums
Partners
Videos
Press
Search
Browse
Sign In
Help
sharad_snh
Adventurer
View all badges
Community Forums
:
About sharad_snh
Latest posts by sharad_snh
Subject
Views
Posted
Re: No response from XPS system cache with generic...
General Technical Discussion
9643
09-11-2016
10:19 PM
Re: Changing compiler order for block design proje...
Simulation and Verification
10044
05-27-2015
02:40 AM
Re: Changing compiler order for block design proje...
Simulation and Verification
10053
05-27-2015
01:42 AM
Changing compiler order for block design projects
Simulation and Verification
10070
05-27-2015
01:10 AM
Re: Power Estimation errors (Duty Cycle must be in...
Vivado Debug and Power Estimation Tools
5750
11-17-2014
12:49 AM
View All ≫
My Accepted Solutions
Subject
Views
Posted
Re: No response from XPS system cache with generic...
General Technical Discussion
9643
09-11-2016
10:19 PM
Re: Problem with Xilinx Divider core
Video and Audio
5757
12-10-2010
01:56 AM
View All ≫
Community Stats
Posts
51
Solutions
2
Kudos Given
1
Kudos Received
0
Member Since
08-24-2008
Contact Me
Online Status
Offline
Date Last Visited
09-12-2016
01:41 AM
Kudos given to
Member
Kudos
gszakacs
1
View All ≫
Latest Tags
use_dsp48
virtex-4
-use_dsp48
blk_mem_gen_v8_2
block design project
BRAM
compile order
dcm
DSP48
Gated Clock
Isim timing simulation
PhysicalDesignRules:372
post route timing simul…
Power Consumption
speed grade
synthesis attribute
Virtex4
View All ≫
