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muravin
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About muravin
Latest posts by muravin
Subject
Views
Posted
TPWS Violation on PCIe PIPECLK
Timing Analysis
211
08-19-2020
07:55 AM
Re: Clock domains with BUFMR driving 2 BUFR+BUFIO
Timing Analysis
239
07-20-2020
07:51 AM
Bit-level deskewing of the clock line instead of t...
Other FPGA Architecture
136
07-19-2020
09:10 PM
Clock domains with BUFMR driving 2 BUFR+BUFIO
Timing Analysis
276
07-19-2020
09:03 PM
Re: set_input_delay does not propagate through the...
Timing Analysis
534
07-19-2020
08:43 PM
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My Accepted Solutions
Subject
Views
Posted
Re: BMM file is not generated after migrating from...
Processor System Design and AXI
8394
03-10-2017
06:24 AM
Re: DDR3 read data corruption on the PS to PL inte...
Processor System Design and AXI
11116
09-26-2016
06:33 AM
Re: passing a user-specific parameters from IPI ca...
Embedded Development Tools
16452
05-20-2016
08:44 AM
Re: managing the number of the VIVADO jobs (server...
Vivado TCL Community
21565
02-10-2016
10:08 AM
Re: moving KC705 design to a custom board
Design Entry
18490
01-07-2016
01:55 PM
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Community Statistics
Posts
926
Solutions
49
Kudos given
9
Kudos received
68
Member Since
11-21-2013
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Date Last Visited
08-19-2020
01:48 PM
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