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ashishd
Xilinx Employee
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About ashishd
Latest posts by ashishd
Subject
Views
Posted
Re: block design to testbench
Xilinx Evaluation Boards
202
11-06-2020
04:37 AM
Re: can not access "open IP example Design.."
Xilinx IP Catalog
166
10-16-2020
10:03 AM
Re: Vivado 2020.1 does not run tcl commands
Vivado TCL Community
480
10-14-2020
11:04 AM
Re: ZCU216 PL DDR4 disabled?
Versal and UltraScale Architecture™
186
10-08-2020
08:46 PM
Re: [Synth 8-1771] for encrypted IP
Synthesis
324
09-29-2020
04:49 AM
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My Accepted Solutions
Subject
Views
Posted
Re: block design to testbench
Xilinx Evaluation Boards
202
11-06-2020
04:37 AM
Re: [Synth 8-1771] for encrypted IP
Synthesis
337
09-29-2020
04:31 AM
Re: Provide "make_wrapper" with a name for the wra...
Vivado TCL Community
395
08-14-2020
01:45 AM
Re: Write project tcl board part and board repo or...
Design Entry
355
08-12-2020
03:32 AM
Re: Block design board part interface 2020.1
Design Entry
212
08-02-2020
11:29 PM
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Community Statistics
Posts
1971
Solutions
296
Kudos given
83
Kudos received
331
Member Since
02-14-2014
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Offline
Date Last Visited
11-06-2020
09:11 AM
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