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aher
Xilinx Employee
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About aher
Latest posts by aher
Subject
Views
Posted
Re: VHDL-2008 target aggregate assignment BUG
Synthesis
103
05-12-2020
06:10 AM
Re: VHDL-2008 target aggregate assignment BUG
Synthesis
159
05-11-2020
11:57 PM
Re: EXCEPTION_ACCESS_VIOLATION
Synthesis
143
05-04-2020
09:03 PM
Re: EXCEPTION_ACCESS_VIOLATION
Synthesis
258
04-29-2020
09:23 PM
Re: Potential bug: [Synth 8-2914] Unsupported RAM ...
Synthesis
174
03-19-2020
01:55 AM
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My Accepted Solutions
Subject
Views
Posted
Re: EXCEPTION_ACCESS_VIOLATION
Synthesis
143
05-04-2020
09:03 PM
Re: Potential bug: [Synth 8-2914] Unsupported RAM ...
Synthesis
174
03-19-2020
01:55 AM
Re: Array of interface in Systemverilog
Synthesis
279
02-25-2020
01:29 AM
Re: Segmentation fault during co-simulation
High-Level Synthesis (HLS)
364
10-25-2019
03:00 AM
Re: 2019.1 Synth Crash with VHDL 2008 generic pack...
Synthesis
334
10-02-2019
08:51 PM
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Community Stats
Posts
800
Solutions
92
Kudos Given
48
Kudos Received
132
Member Since
07-21-2014
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Date Last Visited
05-14-2020
02:01 AM
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