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brasilino
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About brasilino
Latest posts by brasilino
Subject
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Posted
ZynqMPSoC Exclusive access Read not supported on c...
Processor System Design and AXI
94
02-02-2021
12:24 PM
How to make Vivado infer a Master xilinx.com:inter...
Xilinx IP Catalog
451
11-12-2020
11:40 AM
Re: Data transmission from PS to PL using DMA ACP
Processor System Design and AXI
722
11-09-2020
05:54 AM
Re: Topic for user's opensource projects and blog ...
General Technical Discussion
693
11-09-2020
04:44 AM
Re: Using AXI4Stream VIP as ethernet subsystem out...
Processor System Design and AXI
438
11-03-2020
07:06 PM
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My Accepted Solutions
Subject
Views
Posted
Re: Using AXI4Stream VIP as ethernet subsystem out...
Processor System Design and AXI
438
11-03-2020
07:06 PM
Re: How to change default u-boot's dhcp "image.ub"...
Embedded Linux
620
03-09-2020
08:17 AM
Re: Resetting a generated HLS module
High-Level Synthesis (HLS)
2622
01-23-2018
11:15 AM
Re: Can a PCIe endpoint have several outbound requ...
PCIe and CPM
9747
06-30-2016
02:43 PM
Re: speeding up simulations - PCIE example
Simulation and Verification
14914
06-30-2016
11:52 AM
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Member Since
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12:14 PM
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