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	vivado 2014.4 synthesis is taking more time by mtechvlsi17 Newbie in Vivado TCL Community 04-25-2019 0 1	0	1
	Use of HLS/SDS pragmas in OpenCL kernels by abperina Visitor in SDAccel 04-25-2019 0 0	0	0
	HLS ERROR: [XFORM 203-1403] Unsupported enormous number of load/store instructions by jpulliam@cmu Newbie in Vivado High-Level Synthesis (HLS) 04-25-2019 0 2	0	2
	Openamp: Remoteproc Unable to handle kernel paging request by kvkhekale Observer in OpenAMP 04-25-2019 0 0	0	0
	LVDS_25 & 1.8V LVDS input to Artix HR bank by rakeshm55 Explorer in General Technical Discussion 04-25-2019 0 2	0	2
	SPI Loopback by zuzu@123 Observer in Embedded Processor System Design 04-25-2019 0 6	0	6
	Reqirement of extra PL to PS interrupt in Zynq Ultrascale+ by shanish Contributor in Embedded Processor System Design 04-25-2019 0 2	0	2
	VHDL not showing output by carrexev Newbie in Simulation and Verification 04-25-2019 0 6	0	6
	QDMA : WPL REN, WRQ register by rdk Newbie in PCI Express 04-25-2019 0 0	0	0
	Vivado 2018.3: std.env.stop() leads to deadlock of xsim by jens.schoenherr Visitor in Simulation and Verification 04-25-2019 0 1	0	1
	petalinux boot on qemu for cosimulation by hamdi436 Visitor in Embedded Linux 04-25-2019 0 0	0	0
	Vivado HLS 2018.3 text editor size issue by brijendra@iitk.ac.in Observer in Vivado High-Level Synthesis (HLS) 04-25-2019 0 0	0	0
	Varying error behaviour on post synthesis simulation by eldercosta Adventurer in Simulation and Verification 04-25-2019 0 2	0	2
	need latest link for.......Interrupt handling of PL generated interrupt(zynq ultrascale by brijendra@iitk.ac.in Observer in Vivado High-Level Synthesis (HLS) 04-25-2019 0 0	0	0
	How to enable only RX part in transreceive?r by deepg799 Contributor in UltraScale Architecture™ 04-25-2019 0 0	0	0
	"bad phdr da ..." when loading remote app in zynqMP by amsanchez Contributor in OpenAMP 04-25-2019 0 0	0	0
	Vivado HLS 2018.3 text editor color issue by mzrghorbani Visitor in Vivado High-Level Synthesis (HLS) 04-25-2019 0 1	0	1
	XilFPGA and PMU timeout issue. by niklaslindskog Visitor in Embedded Linux 04-25-2019 0 0	0	0
	Zynq UltraScale+MPSoC: Embedded Design Tutorial (UG1209) Design Examle 1 not working. by light11111 Newbie in General Technical Discussion 04-25-2019 0 0	0	0
	creating two parallel loops in Vivado HLS by mkulkarn Visitor in Vivado High-Level Synthesis (HLS) 04-25-2019 0 1	0	1
	"Hidden" timing violation by shaikon Explorer in Timing Analysis 04-25-2019 0 0	0	0
	UG1209 Design Example 1: Using GPIOs, Timers, and Interrupts. Not working in ZCU102 Rev1.1 by light11111 Newbie in Evaluation Boards 04-25-2019 0 0	0	0
	Result is different after insert pragma by icebergyy Visitor in Vivado High-Level Synthesis (HLS) 04-25-2019 0 5	0	5
	Pipe functions: write_pipe, read_pipe, get_pipe_num_packets by mkaiser Participant in SDAccel 04-25-2019 0 2	0	2
	Programming Si570 on custom board by trinadhkosuru Participant in UltraScale Architecture™ 04-25-2019 0 1	0	1
	Location and Numbering of Bitslices by shaikon Explorer in UltraScale Architecture™ 04-25-2019 0 3	0	3
	Export Compliance Verification failed by eglinee Newbie in Welcome & Join 04-25-2019 0 5	0	5
	VCU TRD linux vs windows compile issues by rutabagazuma Visitor in Vivado High-Level Synthesis (HLS) 04-25-2019 0 1	0	1
	Dependence circle error when using Video hls::Resize function to make a quad-screen output by dcc3 Participant in Vivado High-Level Synthesis (HLS) 04-25-2019 0 1	0	1
	DDR SDRAM with XC6SLX9 TQG144 by aravind_s1997 Newbie in Memory Interfaces 04-25-2019 0 2	0	2