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ubenevides
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About ubenevides
Latest posts by ubenevides
Subject
Views
Posted
Re: How to disable specific warnings in HLS?
High-Level Synthesis (HLS)
1015
04-02-2018
07:40 AM
How to disable specific warnings in HLS?
High-Level Synthesis (HLS)
1052
04-02-2018
04:11 AM
Re: No rx_clk_out/tx_clk_out from 10/25G subsystem
Ethernet
1178
03-15-2018
11:38 AM
No rx_clk_out/tx_clk_out from 10/25G subsystem
Ethernet
1245
03-14-2018
11:59 PM
Delayed "Done" signal in SDK reading from AXI lite...
Processor System Design and AXI
513
02-06-2018
07:57 AM
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My Accepted Solutions
Subject
Views
Posted
Re: AXI Stream custom IP Core from autogenerated t...
Design Methodologies and Advanced Tools
4577
06-07-2017
11:23 AM
Re: Vivado 2017.1 mishap creating HDL wrapper
Installation and Licensing
8129
06-03-2017
12:03 PM
Re: XDMA linux driver - design
Other FPGA Architecture
6462
05-30-2017
03:29 PM
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Community Statistics
Posts
103
Solutions
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Kudos given
16
Kudos received
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Member Since
09-22-2016
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Date Last Visited
04-09-2018
01:46 PM
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