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ryana
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About ryana
Latest posts by ryana
Subject
Views
Posted
Re: When will Vivado Simulator support Ultrascale+...
Simulation and Verification
897
12-17-2019
10:17 AM
Re: Clocking issue with HBM2 on U50
Alveo™ Accelerator Cards
606
11-22-2019
03:17 PM
Re: How to build LPDDR4 PHY?
Memory Interfaces and NoC
885
10-02-2019
04:11 PM
Re: MIG IP example design on vivado. is the param...
Memory Interfaces and NoC
962
10-02-2019
04:02 PM
回复： Zynq-7010 DDR3 nonzero additive latency
Memory Interfaces and NoC
759
08-27-2019
12:05 PM
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My Accepted Solutions
Subject
Views
Posted
Re: MPSOC support of 32gbit LPDDR4
Memory Interfaces and NoC
1060
08-16-2019
02:33 PM
Re: about Available PL pin, Zynq Ultrascale+ MpSoc...
Versal and UltraScale Architecture™
900
08-14-2019
01:33 PM
Re: DDR4 SDRAM MIG 2.2
Memory Interfaces and NoC
1281
08-14-2019
11:50 AM
Re: DDR4 v2.2 ECC signals are missing from the Use...
Memory Interfaces and NoC
696
08-07-2019
10:00 AM
Re: How to initialize HBM memory?
Memory Interfaces and NoC
764
08-05-2019
12:23 PM
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Community Statistics
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667
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Member Since
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Date Last Visited
04-15-2021
08:09 PM
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