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frosteyes
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About frosteyes
Latest posts by frosteyes
Subject
Views
Posted
yocto-check-layer fails for 2019.2 layers
Embedded Linux
574
01-17-2020
05:08 AM
Re: Issue with 2019.1 - kernel 4.19 - dwc3 fe20000...
Embedded Linux
1332
09-25-2019
10:59 AM
Re: 2019.1 device tree changed clock for lpd_watch...
Embedded Linux
755
09-25-2019
10:55 AM
Re: Linux tries to disable pll - dpll
Embedded Linux
1045
09-05-2019
03:20 AM
New USB__RESET__MODE in ZynqMP Processing System d...
Processor System Design and AXI
865
09-03-2019
05:37 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Xilinx forum rejects my message
General Technical Discussion
818
12-23-2018
11:56 AM
Re: Devicetree Generator Fails with AXI 10G Ethern...
Embedded Development Tools
5107
01-04-2018
07:28 AM
Re: Set MIO GPIO pin on ZynqMP from FSBL
Embedded Development Tools
5933
11-15-2017
07:06 AM
Re: Timeline for getting the axienet patch in the ...
Embedded Linux
1851
09-26-2017
02:54 AM
Re: zcu102 Rev D1 (ES1) hangs when booting Linux w...
Xilinx Evaluation Boards
6974
09-07-2017
05:50 AM
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Community Statistics
Posts
54
Solutions
5
Kudos given
2
Kudos received
3
Member Since
2016-12-15
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Date Last Visited
01-08-2021
12:03 PM
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anatoli
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stephenm
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Latest Tags
10g
device tree generator
DMA
dts
dtsi
ethernet
zynq ultrascale
axienet
dpll
dwc3
fe200000.dwc3
fsbl
lpd_wdt lpd_watchdog cc…
Reset
usb
USB__RESET__MODE
Vivado
zynqmp_pll_disable
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