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dje666
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About dje666
Latest posts by dje666
Subject
Views
Posted
Re: Aurora duplex reset issues on Artix-7
Xilinx IP Catalog
67
11-11-2020
11:50 PM
Aurora duplex reset issues on Artix-7
Xilinx IP Catalog
154
11-04-2020
02:11 AM
GTP settings for board to boadr Artix-7
Serial Transceivers
170
10-16-2020
09:09 AM
MPSoC PS Peripheral access between A53 ad R5 cores
Processor System Design and AXI
132
10-16-2020
02:58 AM
Artix-7 DMA/PCIe bridge solution that supports sca...
PCIe and CPM
224
10-06-2020
01:02 AM
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My Accepted Solutions
Subject
Views
Posted
回复： Open Camera Error for ZedBoard
AI and Vitis AI
859
10-23-2019
02:17 AM
Re: Generate PWM signal with AXI timer and example...
Processor System Design and AXI
1195
05-08-2019
05:28 AM
Re: Zynq-7000 dual GEMAC and EMIO options
Processor System Design and AXI
537
04-21-2019
02:03 PM
Re: Petalinux on Microblaze ; Kernel panic
Embedded Linux
1067
03-12-2019
05:43 AM
Re: Running Xilinx>Vivado-Integration > Open-Vi...
Vitis Acceleration, SDAccel, SDSoC
926
09-17-2018
05:01 AM
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Community Statistics
Posts
224
Solutions
11
Kudos given
22
Kudos received
11
Member Since
04-21-2017
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Date Last Visited
11-12-2020
03:12 AM
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