Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Account
My Account
Create Account
Sign Out
Search
All
Silicon Devices
Boards and Kits
Intellectual Property
Support
Documentation
Knowledge Base
Community Forums
Partners
Videos
Press
Search
Browse
Sign In
Help
bruce_karaffa
Scholar
View all badges
Community Forums
:
About bruce_karaffa
Latest posts by bruce_karaffa
Subject
Views
Posted
Re: Hold Violations on negedge flops - how to solv...
Timing Analysis
12
04-19-2021
08:07 AM
Re: VHDL : Multiple Declarations of one Component
Synthesis
32
04-19-2021
07:25 AM
Re: VHDL : Multiple Declarations of one Component
Synthesis
64
04-19-2021
06:06 AM
Re: LVDS Deserialize
Other FPGA Architecture
33
04-19-2021
03:33 AM
Re: SP701 spartan 7 - Internal clock using through...
Other FPGA Architecture
29
04-19-2021
03:29 AM
View All ≫
My Accepted Solutions
Subject
Views
Posted
Re: Assignment under multiple single edges is not ...
Xilinx Evaluation Boards
117
04-16-2021
06:20 AM
Re: should be high impedance on signal but showing...
Memory Interfaces and NoC
138
04-15-2021
01:18 PM
Re: Usage of FPGA differential pins on Zynq-7010
FPGA Configuration
120
04-08-2021
03:38 AM
Re: Timing Error - Setup Slack
Timing Analysis
152
03-25-2021
02:37 AM
Re: Timing error on unused DSP48E1 inputs
Other FPGA Architecture
187
03-24-2021
12:31 PM
View All ≫
Community Statistics
Posts
1896
Solutions
206
Kudos given
313
Kudos received
891
Member Since
06-21-2017
Contact Me
Online Status
Online
Date Last Visited
04-19-2021
08:32 AM
Group Hubs for bruce_karaffa
Xilinx Superuser Group
62
View All
Kudos from
Member
Kudos
drjohnsmith
131
leewrigley
2
maps-mpls
8
gbellocchi95
1
Thomas
2
View All ≫
Kudos given to
Member
Kudos
joancab
10
richardhead
21
drjohnsmith
70
egrigor
1
markg@prosensin
g.com
30
View All ≫
Latest Tags
ou can find the
r elooking for the
t
View All ≫
