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pthakare
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About pthakare
Latest posts by pthakare
Subject
Views
Posted
Re: MMCM: Setting "Minimize Output Jitter" will le...
Other FPGA Architecture
106
07-30-2021
01:51 AM
Re: About a new generation of RFSoC
Xilinx Evaluation Boards
119
07-27-2021
08:44 PM
Re: MMCM (Kintex7): Change duty cycle has no effec...
Other FPGA Architecture
118
07-27-2021
05:26 AM
Re: MMCM (Kintex7): Change duty cycle has no effec...
Other FPGA Architecture
152
07-27-2021
04:29 AM
Re: MMCM (Kintex7): Change duty cycle has no effec...
Other FPGA Architecture
186
07-27-2021
03:19 AM
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My Accepted Solutions
Subject
Views
Posted
Re: XADC sample rate depending of channel
Other FPGA Architecture
101
07-27-2021
12:15 AM
Re: RF data converter data format/value question
Versal and UltraScale Architecture™
155
07-25-2021
08:32 PM
Re: rf anlyzer error
Versal and UltraScale Architecture™
199
07-23-2021
07:43 AM
Re: the difference between No DUC 0 to Fs/2 and D...
Versal and UltraScale Architecture™
124
07-23-2021
07:23 AM
Re: Zynq Ultrascale+ RF Data Converter DAC PLL ena...
Versal and UltraScale Architecture™
104
07-14-2021
11:21 PM
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