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zan_zhan@amat.c
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About zan_zhan@amat.com
Latest posts by zan_zhan@amat.com
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quad spi's axi4-lite interface Fmax for Virtex Ult...
Processor System Design and AXI
241
01-03-2021
09:15 AM
About the clock in DMA bridge Subsystem PCIe examp...
PCIe and CPM
402
12-09-2020
01:41 PM
Common Clock Built-in FIFO SRST in Virtex Ultra Pl...
Xilinx IP Catalog
360
09-02-2020
11:43 PM
Re: Use Jtag to see FPGA on-chip voltage&temperatu...
FPGA Configuration
487
08-26-2020
04:30 PM
Use Jtag to see FPGA on-chip voltage&temperature
FPGA Configuration
520
08-26-2020
02:52 PM
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My Accepted Solutions
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回复： Is it possible to change GTY's txpolarity in i...
Serial Transceivers
1645
07-05-2018
11:24 AM
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