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satguy
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About satguy
Latest posts by satguy
Subject
Views
Posted
回复： Vivado HLS start folder
High-Level Synthesis (HLS)
413
02-24-2020
11:52 AM
回复： Vivado HLS start folder
High-Level Synthesis (HLS)
468
02-23-2020
11:19 PM
Vivado HLS start folder
High-Level Synthesis (HLS)
526
02-23-2020
12:06 PM
[BD 41-1629] </zynq_ultra_ps_e_0/SAXIGP6/LPD_LPS_O...
Processor System Design and AXI
437
02-23-2020
09:17 AM
[BD 41-1051] The usage <register> of peripheral .....
Processor System Design and AXI
312
02-23-2020
09:13 AM
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My Accepted Solutions
Subject
Views
Posted
Re: No value for latency in FFT algorithm
Synthesis
459
02-17-2020
10:13 PM
Re: Board definition files
Other FPGA Architecture
463
02-16-2020
09:01 AM
Re: Write TCL misses Verilog header files
Vivado TCL Community
465
02-13-2020
04:18 AM
Re: Virtex-7 versus Kintex-7
FPGA Configuration
328
02-11-2020
05:02 AM
Re: Spartan-7 one pin of VCCO not connected
FPGA Configuration
374
02-10-2020
08:13 AM
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Community Statistics
Posts
225
Solutions
12
Kudos given
45
Kudos received
40
Member Since
04-19-2018
Contact Me
Online Status
Offline
Date Last Visited
02-28-2020
03:34 PM
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khagen@irisdyna
mics.com
1
abouassi
2
dsallen
1
anatoli
2
rpr
1
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gordienkoa1
1
wenchen
1
u4223374
3
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1
claytonr
1
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