Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Fri Jan 6 10:57:43 2017 | Host : cadburry running 64-bit Ubuntu 12.04.5 LTS | Command : report_clocks | Design : APP_FPGA | Device : 7vx415t-ffg1157 | Speed File : -2 PRODUCTION 1.11 2014-09-11 ------------------------------------------------------------------------------------ Clock Report Attributes P: Propagated G: Generated V: Virtual I: Inverted Clock Period(ns) Waveform(ns) Attributes Sources system_i/ETH_0/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk 8.000 {0.000 4.000} P {system_i/ETH_0/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk} system_i/ETH_0/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk 8.000 {0.000 4.000} P {system_i/ETH_0/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk} system_i/mdm_0/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK 33.333 {0.000 16.667} P {system_i/mdm_0/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK} system_i/mdm_0/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE 33.333 {0.000 16.667} P {system_i/mdm_0/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE} system_i/ETH_1/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk 8.000 {0.000 4.000} P {system_i/ETH_1/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk} system_i/ETH_1/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk 8.000 {0.000 4.000} P {system_i/ETH_1/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk} system_i/ETH_2/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk 8.000 {0.000 4.000} P {system_i/ETH_2/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk} system_i/ETH_2/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk 8.000 {0.000 4.000} P {system_i/ETH_2/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk} system_i/ETH_3/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk 8.000 {0.000 4.000} P {system_i/ETH_3/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk} system_i/ETH_3/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk 8.000 {0.000 4.000} P {system_i/ETH_3/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk} RX_CLK_P 5.000 {0.000 2.500} P {RX_CLK_P} TX_CLK_P 5.000 {0.000 2.500} P,G {TX_CLK_P} CLK_200_P 5.000 {0.000 2.500} P {CLK_200_P} RIGHT_P[45] 8.000 {0.000 4.000} P {RIGHT_P[45]} RIGHT_P[46] 8.000 {0.000 4.000} P {RIGHT_P[46]} RIGHT_N[32] 8.000 {0.000 4.000} P {RIGHT_N[32]} RIGHT_P[28] 8.000 {0.000 4.000} P {RIGHT_P[28]} RIGHT_P[19] 8.000 {0.000 4.000} P {RIGHT_P[19]} RIGHT_P[25] 8.000 {0.000 4.000} P {RIGHT_P[25]} RIGHT_P[7] 8.000 {0.000 4.000} P {RIGHT_P[7]} RIGHT_N[9] 8.000 {0.000 4.000} P {RIGHT_N[9]} CLKFBIN 10.000 {0.000 5.000} P,G {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKFBOUT} int_clk_200_mmcm 5.000 {0.000 2.500} P,G {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKOUT3} temac_clk_125 8.000 {0.000 4.000} P,G {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKOUT5} int_CLKFB 10.000 {0.000 5.000} P,G {clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKFBOUT} int_RX_CLK180 5.000 {2.500 5.000} P,G {clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKOUT2} pll_clkfbout 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} freq_refclk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} mem_refclk 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} sync_pulse 20.000 {0.547 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} pll_clk3_out 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} mmcm_clkfbout 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKFBOUT} clk_ref_mmcm_400 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK} oserdes_clk 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK} oserdes_clk_1 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} oserdes_clk_2 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} oserdes_clk_3 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} oserdes_clk_4 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} oserdes_clk_5 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} oserdes_clk_6 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} oserdes_clk_7 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK} oserdes_clk_8 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK} oserdes_clk_9 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} oserdes_clk_10 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} oserdes_clk_11 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} clk_pll_i 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT} mmcm_ps_clk_bufg_in 10.000 {0.000 5.000} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT5} iserdes_clkdiv 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} iserdes_clkdiv_1 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_1 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} iserdes_clkdiv_2 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_2 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} iserdes_clkdiv_3 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_3 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} oserdes_clkdiv_4 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} oserdes_clkdiv_5 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} oserdes_clkdiv_6 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} oserdes_clkdiv_7 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} iserdes_clkdiv_4 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_8 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} iserdes_clkdiv_5 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_9 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} iserdes_clkdiv_6 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_10 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} iserdes_clkdiv_7 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_11 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} ==================================================== Generated Clocks ==================================================== Generated Clock : TX_CLK_P Master Source : clk_infrastructure_i/com_fpga_tx_clk_oddr/s7_oddr_gen.ODDR_inst/C Master Clock : CLK_200_P Divide By : 1 Generated Sources : {TX_CLK_P} Generated Clock : CLKFBIN Master Source : clk_infrastructure_i/MB_SYSTEM_MMCM/CLKIN1 Master Clock : CLK_200_P Edges : {1 2 3} Edge Shifts(ns) : {0.000 2.500 5.000} Generated Sources : {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKFBOUT} Generated Clock : int_clk_200_mmcm Master Source : clk_infrastructure_i/MB_SYSTEM_MMCM/CLKIN1 Master Clock : CLK_200_P Multiply By : 1 Generated Sources : {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKOUT3} Generated Clock : temac_clk_125 Master Source : clk_infrastructure_i/MB_SYSTEM_MMCM/CLKIN1 Master Clock : CLK_200_P Edges : {1 2 3} Edge Shifts(ns) : {0.000 1.500 3.000} Generated Sources : {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKOUT5} Generated Clock : int_CLKFB Master Source : clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKIN1 Master Clock : RX_CLK_P Edges : {1 2 3} Edge Shifts(ns) : {0.000 2.500 5.000} Generated Sources : {clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKFBOUT} Generated Clock : int_RX_CLK180 Master Source : clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKIN1 Master Clock : RX_CLK_P Edges : {1 2 3} Edge Shifts(ns) : {2.500 2.500 2.500} Generated Sources : {clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKOUT2} Generated Clock : pll_clkfbout Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Master Clock : int_clk_200_mmcm Multiply By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} Generated Clock : freq_refclk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Master Clock : int_clk_200_mmcm Edges : {1 2 3} Edge Shifts(ns) : {1.172 -0.703 -2.578} Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} Generated Clock : mem_refclk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Master Clock : int_clk_200_mmcm Multiply By : 4 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} Generated Clock : sync_pulse Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Master Clock : int_clk_200_mmcm Edges : {1 2 3} Edge Shifts(ns) : {0.547 -0.703 15.547} Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} Generated Clock : pll_clk3_out Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Master Clock : int_clk_200_mmcm Multiply By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} Generated Clock : mmcm_clkfbout Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKIN1 Master Clock : int_clk_200_mmcm Multiply By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKFBOUT} Generated Clock : clk_ref_mmcm_400 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKIN1 Master Clock : int_clk_200_mmcm Multiply By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_1 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_2 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_3 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} Generated Clock : oserdes_clk_4 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} Generated Clock : oserdes_clk_5 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} Generated Clock : oserdes_clk_6 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} Generated Clock : oserdes_clk_7 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_8 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_9 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_10 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_11 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} Generated Clock : clk_pll_i Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1 Master Clock : pll_clk3_out Multiply By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT} Generated Clock : mmcm_ps_clk_bufg_in Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1 Master Clock : pll_clk3_out Edges : {1 2 3} Edge Shifts(ns) : {0.000 2.500 5.000} Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT5} Generated Clock : iserdes_clkdiv Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK Master Clock : oserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_1 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_1 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK Master Clock : oserdes_clk_1 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_2 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_2 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK Master Clock : oserdes_clk_2 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_3 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_3 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK Master Clock : oserdes_clk_3 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} Generated Clock : oserdes_clkdiv_4 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK Master Clock : oserdes_clk_4 Divide By : 4 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} Generated Clock : oserdes_clkdiv_5 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK Master Clock : oserdes_clk_5 Divide By : 4 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} Generated Clock : oserdes_clkdiv_6 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK Master Clock : oserdes_clk_6 Divide By : 4 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} Generated Clock : oserdes_clkdiv_7 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK Master Clock : oserdes_clk_7 Divide By : 4 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_4 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_8 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK Master Clock : oserdes_clk_8 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_5 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_9 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK Master Clock : oserdes_clk_9 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_6 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_10 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK Master Clock : oserdes_clk_10 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_7 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_11 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK Master Clock : oserdes_clk_11 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} ==================================================== User Uncertainty ==================================================== ==================================================== User Jitter ==================================================== Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Fri Jan 6 10:57:52 2017 | Host : cadburry running 64-bit Ubuntu 12.04.5 LTS | Command : report_clocks | Design : APP_FPGA | Device : 7vx415t-ffg1157 | Speed File : -2 PRODUCTION 1.11 2014-09-11 ------------------------------------------------------------------------------------ Clock Report Attributes P: Propagated G: Generated V: Virtual I: Inverted Clock Period(ns) Waveform(ns) Attributes Sources system_i/ETH_0/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk 8.000 {0.000 4.000} P {system_i/ETH_0/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk} system_i/ETH_0/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk 8.000 {0.000 4.000} P {system_i/ETH_0/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk} system_i/mdm_0/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK 33.333 {0.000 16.667} P {system_i/mdm_0/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK} system_i/mdm_0/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE 33.333 {0.000 16.667} P {system_i/mdm_0/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE} system_i/ETH_1/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk 8.000 {0.000 4.000} P {system_i/ETH_1/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk} system_i/ETH_1/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk 8.000 {0.000 4.000} P {system_i/ETH_1/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk} system_i/ETH_2/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk 8.000 {0.000 4.000} P {system_i/ETH_2/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk} system_i/ETH_2/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk 8.000 {0.000 4.000} P {system_i/ETH_2/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk} system_i/ETH_3/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk 8.000 {0.000 4.000} P {system_i/ETH_3/axi_ethernet_0/U0/eth_mac/U0/gmii_rx_clk} system_i/ETH_3/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk 8.000 {0.000 4.000} P {system_i/ETH_3/axi_ethernet_0/U0/eth_mac/U0/mii_tx_clk} RX_CLK_P 5.000 {0.000 2.500} P {RX_CLK_P} TX_CLK_P 5.000 {0.000 2.500} P,G {TX_CLK_P} CLK_200_P 5.000 {0.000 2.500} P {CLK_200_P} RIGHT_P[45] 8.000 {0.000 4.000} P {RIGHT_P[45]} RIGHT_P[46] 8.000 {0.000 4.000} P {RIGHT_P[46]} RIGHT_N[32] 8.000 {0.000 4.000} P {RIGHT_N[32]} RIGHT_P[28] 8.000 {0.000 4.000} P {RIGHT_P[28]} RIGHT_P[19] 8.000 {0.000 4.000} P {RIGHT_P[19]} RIGHT_P[25] 8.000 {0.000 4.000} P {RIGHT_P[25]} RIGHT_P[7] 8.000 {0.000 4.000} P {RIGHT_P[7]} RIGHT_N[9] 8.000 {0.000 4.000} P {RIGHT_N[9]} CLKFBIN 10.000 {0.000 5.000} P,G {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKFBOUT} int_clk_200_mmcm 5.000 {0.000 2.500} P,G {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKOUT3} temac_clk_125 8.000 {0.000 4.000} P,G {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKOUT5} int_CLKFB 10.000 {0.000 5.000} P,G {clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKFBOUT} int_RX_CLK180 5.000 {2.500 5.000} P,G {clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKOUT2} pll_clkfbout 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} freq_refclk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} mem_refclk 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} sync_pulse 20.000 {0.547 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} pll_clk3_out 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} mmcm_clkfbout 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKFBOUT} clk_ref_mmcm_400 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK} oserdes_clk 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK} oserdes_clk_1 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} oserdes_clk_2 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} oserdes_clk_3 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} oserdes_clk_4 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} oserdes_clk_5 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} oserdes_clk_6 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} oserdes_clk_7 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK} oserdes_clk_8 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK} oserdes_clk_9 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} oserdes_clk_10 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.250 {1.172 1.797} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} oserdes_clk_11 1.250 {0.000 0.625} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} clk_pll_i 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT} mmcm_ps_clk_bufg_in 10.000 {0.000 5.000} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT5} iserdes_clkdiv 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} iserdes_clkdiv_1 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_1 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} iserdes_clkdiv_2 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_2 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} iserdes_clkdiv_3 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_3 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} oserdes_clkdiv_4 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} oserdes_clkdiv_5 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} oserdes_clkdiv_6 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} oserdes_clkdiv_7 5.000 {0.000 2.500} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} iserdes_clkdiv_4 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_8 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} iserdes_clkdiv_5 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_9 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} iserdes_clkdiv_6 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_10 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} iserdes_clkdiv_7 2.500 {1.172 2.422} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} oserdes_clkdiv_11 2.500 {0.000 1.250} P,G {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} ==================================================== Generated Clocks ==================================================== Generated Clock : TX_CLK_P Master Source : clk_infrastructure_i/com_fpga_tx_clk_oddr/s7_oddr_gen.ODDR_inst/C Master Clock : CLK_200_P Divide By : 1 Generated Sources : {TX_CLK_P} Generated Clock : CLKFBIN Master Source : clk_infrastructure_i/MB_SYSTEM_MMCM/CLKIN1 Master Clock : CLK_200_P Edges : {1 2 3} Edge Shifts(ns) : {0.000 2.500 5.000} Generated Sources : {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKFBOUT} Generated Clock : int_clk_200_mmcm Master Source : clk_infrastructure_i/MB_SYSTEM_MMCM/CLKIN1 Master Clock : CLK_200_P Multiply By : 1 Generated Sources : {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKOUT3} Generated Clock : temac_clk_125 Master Source : clk_infrastructure_i/MB_SYSTEM_MMCM/CLKIN1 Master Clock : CLK_200_P Edges : {1 2 3} Edge Shifts(ns) : {0.000 1.500 3.000} Generated Sources : {clk_infrastructure_i/MB_SYSTEM_MMCM/CLKOUT5} Generated Clock : int_CLKFB Master Source : clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKIN1 Master Clock : RX_CLK_P Edges : {1 2 3} Edge Shifts(ns) : {0.000 2.500 5.000} Generated Sources : {clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKFBOUT} Generated Clock : int_RX_CLK180 Master Source : clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKIN1 Master Clock : RX_CLK_P Edges : {1 2 3} Edge Shifts(ns) : {2.500 2.500 2.500} Generated Sources : {clk_infrastructure_i/com_fpga_interfpga_rx.interfpga_rxclk_i/RX_CLK_DCM/s7_gen.MMCME2_ADV_inst/CLKOUT2} Generated Clock : pll_clkfbout Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Master Clock : int_clk_200_mmcm Multiply By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} Generated Clock : freq_refclk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Master Clock : int_clk_200_mmcm Edges : {1 2 3} Edge Shifts(ns) : {1.172 -0.703 -2.578} Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} Generated Clock : mem_refclk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Master Clock : int_clk_200_mmcm Multiply By : 4 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} Generated Clock : sync_pulse Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Master Clock : int_clk_200_mmcm Edges : {1 2 3} Edge Shifts(ns) : {0.547 -0.703 15.547} Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} Generated Clock : pll_clk3_out Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Master Clock : int_clk_200_mmcm Multiply By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} Generated Clock : mmcm_clkfbout Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKIN1 Master Clock : int_clk_200_mmcm Multiply By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKFBOUT} Generated Clock : clk_ref_mmcm_400 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKIN1 Master Clock : int_clk_200_mmcm Multiply By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_1 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_2 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_3 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} Generated Clock : oserdes_clk_4 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} Generated Clock : oserdes_clk_5 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} Generated Clock : oserdes_clk_6 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} Generated Clock : oserdes_clk_7 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_8 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_9 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_10 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/FREQREFCLK Master Clock : freq_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} Generated Clock : oserdes_clk_11 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK Master Clock : mem_refclk Divide By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} Generated Clock : clk_pll_i Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1 Master Clock : pll_clk3_out Multiply By : 1 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT} Generated Clock : mmcm_ps_clk_bufg_in Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1 Master Clock : pll_clk3_out Edges : {1 2 3} Edge Shifts(ns) : {0.000 2.500 5.000} Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT5} Generated Clock : iserdes_clkdiv Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK Master Clock : oserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_1 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_1 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK Master Clock : oserdes_clk_1 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_2 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_2 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK Master Clock : oserdes_clk_2 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_3 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_3 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK Master Clock : oserdes_clk_3 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} Generated Clock : oserdes_clkdiv_4 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK Master Clock : oserdes_clk_4 Divide By : 4 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} Generated Clock : oserdes_clkdiv_5 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK Master Clock : oserdes_clk_5 Divide By : 4 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} Generated Clock : oserdes_clkdiv_6 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK Master Clock : oserdes_clk_6 Divide By : 4 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} Generated Clock : oserdes_clkdiv_7 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK Master Clock : oserdes_clk_7 Divide By : 4 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_4 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_8 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK Master Clock : oserdes_clk_8 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_5 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_9 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK Master Clock : oserdes_clk_9 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_6 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_10 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK Master Clock : oserdes_clk_10 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} Generated Clock : iserdes_clkdiv_7 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} Generated Clock : oserdes_clkdiv_11 Master Source : system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK Master Clock : oserdes_clk_11 Divide By : 2 Generated Sources : {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} ==================================================== User Uncertainty ==================================================== ==================================================== User Jitter ====================================================