source make_project.tcl # set project_name "1_led_blink" # source projects/$project_name/block_design.tcl ## set part_name xc7z010clg400-1 ## set bd_path tmp/$project_name/$project_name.srcs/sources_1/bd/system ## file delete -force tmp/$project_name ## create_project $project_name tmp/$project_name -part $part_name INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Xilinx_Vivado_SDK_2017.4_1216_1/Vivado/2017.4/data/ip'. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 6351.996 ; gain = 0.000 ; free physical = 71 ; free virtual = 3539 ## create_bd_design system Wrote : create_bd_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 6351.996 ; gain = 0.000 ; free physical = 87 ; free virtual = 3517 ## source cfg/ports.tcl ### create_bd_port -dir I -from 13 -to 0 adc_dat_a_i ### create_bd_port -dir I -from 13 -to 0 adc_dat_b_i ### create_bd_port -dir I adc_clk_p_i ### create_bd_port -dir I adc_clk_n_i ### create_bd_port -dir O adc_enc_p_o ### create_bd_port -dir O adc_enc_n_o ### create_bd_port -dir O adc_csn_o ### create_bd_port -dir O -from 13 -to 0 dac_dat_o ### create_bd_port -dir O dac_clk_o ### create_bd_port -dir O dac_rst_o ### create_bd_port -dir O dac_sel_o ### create_bd_port -dir O dac_wrt_o ### create_bd_port -dir O -from 3 -to 0 dac_pwm_o ### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn ### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 ### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1 ### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9 ### create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 ### create_bd_port -dir IO -from 7 -to 0 exp_p_tri_io ### create_bd_port -dir IO -from 7 -to 0 exp_n_tri_io ### create_bd_port -dir O -from 1 -to 0 daisy_p_o ### create_bd_port -dir O -from 1 -to 0 daisy_n_o ### create_bd_port -dir I -from 1 -to 0 daisy_p_i ### create_bd_port -dir I -from 1 -to 0 daisy_n_i ### create_bd_port -dir O -from 7 -to 0 led_o ## set_property IP_REPO_PATHS tmp/cores [current_project] ## update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/chris/redpitaya_guide/tmp/cores'. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. ## startgroup ## create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7 processing_system7_0 ## set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] [get_bd_cells processing_system7_0] ## set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {cfg/red_pitaya.xml}] [get_bd_cells processing_system7_0] INFO: [PS7-1] Applying Custom Preset cfg/red_pitaya.xml... ## endgroup ## startgroup ## create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_0 ## set_property -dict [list CONFIG.C_SIZE {2}] [get_bd_cells util_ds_buf_0] ## create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_1 ## set_property -dict [list CONFIG.C_SIZE {2}] [get_bd_cells util_ds_buf_1] ## create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_2 ## set_property -dict [list CONFIG.C_SIZE {2}] [get_bd_cells util_ds_buf_2] ## set_property -dict [list CONFIG.C_BUF_TYPE {OBUFDS}] [get_bd_cells util_ds_buf_2] ## endgroup ## startgroup ## create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary c_counter_binary_0 ## set_property -dict [list CONFIG.Output_Width {32}] [get_bd_cells c_counter_binary_0] ## endgroup ## startgroup ## create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_0 ## set_property -dict [list CONFIG.DIN_TO {26} CONFIG.DIN_FROM {26} CONFIG.DIN_FROM {26} CONFIG.DOUT_WIDTH {1}] [get_bd_cells xlslice_0] ## endgroup ## set_property LEFT 0 [get_bd_ports led_o] ## connect_bd_net [get_bd_ports adc_clk_p_i] [get_bd_pins util_ds_buf_0/IBUF_DS_P] WARNING: [BD 41-1306] The connection to interface pin /util_ds_buf_0/IBUF_DS_P is being overridden by the user. This pin will not be connected as a part of interface connection CLK_IN_D ## connect_bd_net [get_bd_ports adc_clk_n_i] [get_bd_pins util_ds_buf_0/IBUF_DS_N] WARNING: [BD 41-1306] The connection to interface pin /util_ds_buf_0/IBUF_DS_N is being overridden by the user. This pin will not be connected as a part of interface connection CLK_IN_D ## connect_bd_net [get_bd_ports daisy_p_i] [get_bd_pins util_ds_buf_1/IBUF_DS_P] WARNING: [BD 41-1306] The connection to interface pin /util_ds_buf_1/IBUF_DS_P is being overridden by the user. This pin will not be connected as a part of interface connection CLK_IN_D ## connect_bd_net [get_bd_ports daisy_n_i] [get_bd_pins util_ds_buf_1/IBUF_DS_N] WARNING: [BD 41-1306] The connection to interface pin /util_ds_buf_1/IBUF_DS_N is being overridden by the user. This pin will not be connected as a part of interface connection CLK_IN_D ## connect_bd_net [get_bd_ports daisy_p_o] [get_bd_pins util_ds_buf_2/OBUF_DS_P] ## connect_bd_net [get_bd_ports daisy_n_o] [get_bd_pins util_ds_buf_2/OBUF_DS_N] ## connect_bd_net [get_bd_pins util_ds_buf_1/IBUF_OUT] [get_bd_pins util_ds_buf_2/OBUF_IN] ## apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] ## connect_bd_net [get_bd_pins c_counter_binary_0/Q] [get_bd_pins xlslice_0/Din] ## connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins c_counter_binary_0/CLK] ## connect_bd_net [get_bd_ports led_o] [get_bd_pins xlslice_0/Dout] ## connect_bd_net [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0] ## connect_bd_net [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0] ## generate_target all [get_files $bd_path/system.bd] WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream Wrote : Wrote : VHDL Output written to : /home/chris/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/synth/system.v VHDL Output written to : /home/chris/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/sim/system.v VHDL Output written to : /home/chris/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hdl/system_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block c_counter_binary_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block xlslice_0 . Exporting to file /home/chris/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hw_handoff/system.hwh Generated Block Design Tcl file /home/chris/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl Generated Hardware Definition File /home/chris/redpitaya_guide/tmp/1_led_blink/1_led_blink.srcs/sources_1/bd/system/synth/system.hwdef generate_target: Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 6353.746 ; gain = 1.750 ; free physical = 74 ; free virtual = 3448 ## make_wrapper -files [get_files $bd_path/system.bd] -top ## add_files -norecurse $bd_path/hdl/system_wrapper.v ## set files [glob -nocomplain projects/$project_name/*.v projects/$project_name/*.sv] ## if {[llength $files] > 0} { ## add_files -norecurse $files ## } ## set files [glob -nocomplain cfg/*.xdc] ## if {[llength $files] > 0} { ## add_files -norecurse -fileset constrs_1 $files ## } ## set_property VERILOG_DEFINE {TOOL_VIVADO} [current_fileset] ## set_property STRATEGY Flow_PerfOptimized_High [get_runs synth_1] ## set_property STRATEGY Performance_NetDelay_high [get_runs impl_1] update_compile_order -fileset sources_1 launch_runs synth_1 -scripts_only launch_runs impl_1 -scripts_only reset_run synth_1 launch_runs impl_1 -to_step write_bitstream -scripts_only