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patocarr
Teacher
Teacher
8,210 Views
Registered: ‎01-28-2008

Tandem PROM on Zynq - DRC place errors.

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Hi folks,

  I'm trying to enable Tandem PROM mode in a Zynq xc7z045 design and running
into place errors, with the following DRC error message(s):

[DRC 23-20] Rule violation (HDTC-6) Non-stage-one logic illegally placed - Non-stage-one logic 'gen_pl_ddr3.inst_mq_pb/inst_ddr3/u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo' is placed at site 'IN_FIFO_X1Y16' inside stage one Pblock 'pcie_7x_mmcm_pblock_boot'. Non-stage-one logic should not be placed inside a stage one region.



  The PCIe block is next to a MIG DDR3 block, and the sub-blocks causing these
errors are inside the automatically generated pcie_7x_mmcm_pblock_boot,
including the IN_FIFO*, OUT_FIFO*, PHASER_*, etc. used by MIG. The message
repeats for all the 19 memory sub-blocks in that mmcm pblock.

  The error seems incorrect by saying "Non-stage-one logic illegally placed",
since this logic *should be* stage-one logic as shown in the post-opt
checkpoint screenshots.

  Any pointers about what to check would be greatly appreciated.

Thanks in advance,
-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

Screenshot-2016-04-21_17.21.42.png
Screenshot-2016-04-21_17.22.01.png
Screenshot-2016-04-21_17.22.20.png
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patocarr
Teacher
Teacher
15,548 Views
Registered: ‎01-28-2008

Answering myself after finding the cause of the DRC. The PCIe core uses the MMCM in the clock region right above it, and this stage 1 block contains the DDR3 controller that uses those memory components (IN-FIFO, PHASER, etc.). By stage 1 using the MMCM, those components are unavailable for stage 2 usage.

 

From PG054, April 6, 2016, page 175 - Tandem resource restrictions:

 

The PCIe IP uses a single MMCM and associated BUFGs to generate the required clocks.
Unused resources within these frames are not available to the user application (stage
2). Additional resources within the clocking frame are the PLL, Phaser, and INOUT FIFO.

 

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

View solution in original post

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2 Replies
patocarr
Teacher
Teacher
15,549 Views
Registered: ‎01-28-2008

Answering myself after finding the cause of the DRC. The PCIe core uses the MMCM in the clock region right above it, and this stage 1 block contains the DDR3 controller that uses those memory components (IN-FIFO, PHASER, etc.). By stage 1 using the MMCM, those components are unavailable for stage 2 usage.

 

From PG054, April 6, 2016, page 175 - Tandem resource restrictions:

 

The PCIe IP uses a single MMCM and associated BUFGs to generate the required clocks.
Unused resources within these frames are not available to the user application (stage
2). Additional resources within the clocking frame are the PLL, Phaser, and INOUT FIFO.

 

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

View solution in original post

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nilsun9
Visitor
Visitor
3,544 Views
Registered: ‎12-13-2016

HI patocarr,

Can you please elaborate more? I am getting the same problem but not able to solve it. It would be great if you can elaborate it.

Thanks in Advance.

Nilsun

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