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chris0622
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Registered: ‎09-22-2019

shift hundreds of bits in one clock

Hi ,

I'm doing RTL code for some functions, and then I encountered a problem.
Does anybody know if it will happen timing violation if I shift 500 bits  to a register in one clock .
If yes, what is the limit of bits that I can shift in one clock.

EX:
test.PNG
Thank you!! 

 

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drjohnsmith
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Registered: ‎07-09-2009

I'm sorry, this makes no sense,

what language are you designing in , HLS , RTL, C ?

May be my mantra might be of help here

"remember you describing hardware you want the tools to make"

   if you can not design ( at least in outline ) the logic circuits, then the tools are unlikely to have much luck 

 

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chris0622
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Registered: ‎09-22-2019

Hi drjohnsmith,

The language I use is verilog(RTL).

Thank you for your reply!

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drjohnsmith
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@chris0622 

have you edited your question,

   it clearly has verilog in it , which is did not.

thank you

   that now makes my question seem stupid.

 

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drjohnsmith
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Yes

 

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drjohnsmith
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so what you are looking for is 500, 2 to 1 multiplexers, 

   not exactly hard

 

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joancab
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Registered: ‎05-11-2015

A shift register doesn't shift one by one until the number you want. So it's the same to shift one position than one thousand.

Said that, be aware of:

- Operations on large registers mean many operations in parallel, and that can produce congestion and timing failing (but not the shift amount itself)

- Functions using large registers create busses that also are a magnet for congestions that reveal as placement errors or timing failures.

chris0622
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Registered: ‎09-22-2019

Hi, 

First, thank you all for your replies. I benefited a lot !

The last question. if I code like this below , it wouldn't  produce congestion or timing violation. right?

擷取2.PNG

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drjohnsmith
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Registered: ‎07-09-2009

its impossibel to say

If youw ere in a small artix 7, or a CPLD, you might have problems

  in an ultra scale you are unlikely to , unless the design is already full

 

Its like saying, is this plate of food enough ? 

   depends on the recipiant !

 

BTW: Your in Verilog, not my favorit language,

    but may be some one else can jump in , that if (!rstn) || init ) begin

       looks strange

 

 

 

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joancab
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Registered: ‎05-11-2015

The !rstn is for the async reset. The || init is unusual, but can't see the problem, it just keeps it in reset on top of the rstn

drjohnsmith
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Registered: ‎07-09-2009

Thank you

I just had doubts, so thought I'd ask

 

BTW: @chris0622 

why do you need asynchronous reset,

    you have a constant clock ?

An asynchronous reset has potential to just adds routing / congestion which I know you are concerned about 

why do you need a synchronous reset ? 

   FPGA s power up to a known / defined state .

 

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chris0622
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Hi,
the reason that I use asyc reset is I want to save the cost of resources .

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drjohnsmith
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Why do you think that using asynchronous reset saves the resources / cost ?

https://www.xilinx.com/support/documentation/white_papers/wp272.pdf

https://www.embedded.com/asynchronous-reset-synchronization-and-distribution-asics-and-fpgas/

 

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chris0622
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Registered: ‎09-22-2019

Since  Most  manufacturers  have  asynchronous  reset ports in their target libraries , I think this way can save resources...

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drjohnsmith
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Registered: ‎07-09-2009

Thinking is not knowing,

   and ASICs are not FPGAs 

And this is a FPGA companies site,

 

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richardhead
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@chris0622 

Xilinx have recommended avoiding using a reset whenever possible for a long time and Im pretty sure it still holds for the more modern families: https://www.xilinx.com/support/documentation/white_papers/wp272.pdf

In Xilinx FPGAs particularly, you tend to run out of routing resources before logic resources, and that unneeded reset is just using the routing.