We designed subblocks by using the Vivado HLS. RTL kernel wizard from the vitis packages all verilog files into the xo. With the vitis flow, we met the 260 MHz including kernel and alveo u250 shell.
We are trying to increase clock frequency up to 300MHz since we already used that clock to generate all hls subblocks from the Vivado HLS (2020.01). To exploit the ooc (out-of context) for the hls subblock, we set the ooc from the vivado which is executed by RTL kernel wizard. When we use the source (*.rtl) packaging from the vivado, upto 260 MHz timing met achieved. However, when we use the dcp-based xo packaing from the vivado, inter-clock timing violation occurs due to the ooc clock.
From the attached image, there are ap_clk from the left side (dcp-based xo packaking case). We already removed clock constraint from the ooc subblock from the vivado. But only the top block has the clock constraint (in this example, 280 MHz was given)
From the vitis flow, we can set the implementation options to explore the performance. Similar to that, can we set the synthesis options for the rtl kernels ? In fact, I already set the synthesis strategy only for the rtl kernel top blocks. However, I want to set the strategy for the subblocks which are generated by hls tools.
Q2) How can we use the ooc from the vitis flow (rtl kernrel) without the clock problem?