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Regular Contributor
yhubert
Posts: 57
Registered: ‎11-15-2010
0

LVPECL IOSTANDARD

Hi,

 

It seems that LVPECL IO Standard disappeared from 7-series FPGA!

 

What is the IOstandard available that I can use as a subtitute?

I need a 300MHz Diff input 800 mVpp - 2.5Vcm compatible.

 

In the same bank I have 100Ohms- LVDS diff inputs and I read that I need to supply Vcco of the bank at 1.8V for a correct use of the 100 ohms diff term. Is that true?

 

What are the IOStandard I could use (in a bank supplied at 3.3V) for LVDS and LVPECL inputs ?

 

 

Moderator
jschimek
Posts: 111
Registered: ‎08-02-2007
0

Re: LVPECL IOSTANDARD

Yhubert,

 

To use DIFF_TERM the 100ohm internal diff termination for LVDS, you would need a 1.8v Vcco for HP banks, or a 2.5v Vcco for a HR bank.  Since you mention 1.8v I'm assuming a HP bank, which will have clamp diodes that will restrict you from having a 2.5v Vcm. 

 

This is all covered in the SelectIO userguide:

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

Diff_term - page 47

 

The data sheet shows valid input levels by standard

http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf

starting page 9.

 

Regards,

Jon

 

 

Regular Visitor
paubert
Posts: 16
Registered: ‎03-25-2009
0

Re: LVPECL IOSTANDARD

Hi,


yhubert wrote:

Hi,

It seems that LVPECL IO Standard disappeared from 7-series FPGA!


Indeed!


What is the IOstandard available that I can use as a subtitute?

I need a 300MHz Diff input 800 mVpp - 2.5Vcm compatible.


Then you are out of luck, the Vcm range for Kintex-7 seems to be 0.3 to 1.425V for LVDS, the later value giving a rather small margin from the nominal 1.25V value. This said, 2.5V is a surprisingly high value: for LVPECL, Vcm is typically 1.3V below supply.


In the same bank I have 100Ohms- LVDS diff inputs and I read that I need to supply Vcco of the bank at 1.8V for a correct use of the 100 ohms diff term. Is that true?

What are the IOStandard I could use (in a bank supplied at 3.3V) for LVDS and LVPECL inputs ?


Are you sure that you don't mix up HP and HR banks?

At least HR banks need 2.5V for diff_term to work and can operate with Vcco up to 3.3V.

Regular Contributor
yhubert
Posts: 57
Registered: ‎11-15-2010
0

Re: LVPECL IOSTANDARD

Thanks to both of you.

 

I'm a bit surprised by those limitations and I'll have to give a deep insight into those rules before validating my design.

Regular Contributor
yhubert
Posts: 57
Registered: ‎11-15-2010
0

Re: LVPECL IOSTANDARD

Can you also please confirm that "inner output series termination" is not available anymore for LVCMOS33 (because there is no output series termination inside the FPGA for HR banks).

In other words: Does the Output Series resistors have to be outside the FPGA for HR banks?

Moderator
jschimek
Posts: 111
Registered: ‎08-02-2007
0

Re: LVPECL IOSTANDARD

Yhubert,

 

Using the DRIVE attribute, you are essentially controlling the output impedance.   A 6mA or 8mA drive will get you pretty close to an impedance matched driver for a 50ohm trace.

 

Regards,

Jon

Regular Contributor
yhubert
Posts: 57
Registered: ‎11-15-2010
0

Re: LVPECL IOSTANDARD

Thx Jon, but the closest Impedance to 50 ohms I can get is arround 30 ohms with LVCMOS33 slow 4mA. I think I'll need the external R.

Moderator
jschimek
Posts: 111
Registered: ‎08-02-2007
0

Re: LVPECL IOSTANDARD

Are you just worried about reflections?  You may want to throw down a quick IBIS sim as I bet there is a solution that will work for you.

 

Regards,

Jon

Regular Contributor
brimdavis
Posts: 56
Registered: ‎04-26-2012
0

Re: LVPECL IOSTANDARD

> It seems that LVPECL IO Standard disappeared from 7-series FPGA!

> What is the IOstandard available that I can use as a subtitute?

> I need a 300MHz Diff input 800 mVpp - 2.5Vcm compatible.

 

See OnSemi AN1568-D for some typical resistive divider techniques:

"Figure 11 Interfacing 2.5 V LVPECL to LVDS With Series RS and External 100 Ohm Termination Resistor"

"Figure 15. Interfacing LVPECL to LVDS with Internal 100 Ohm  Termination Resistor"

http://www.onsemi.com/pub_link/Collateral/AN1568-D.PDF

 

You will want to juggle the resistor values to provide the required attenuation and a good back termination, as described near Figure 15 in that application note.

 

ECL drivers have low output impedance and extremely fast edges; without any back termination, one will typically have problems with re-reflections off the driver when driving the huge Cin of a typical FPGA.

 

- Brian

Contributor
mjholmes99
Posts: 31
Registered: ‎08-07-2008

Re: LVPECL IOSTANDARD

I had a similar situation with a V6 design. I had clock and data coming from an EP445 1:8 deserializer at LVPECL. The data, unfortunately, is single ended.

 

Rather than try some kludgey attempt to bring in single ended LVPECL to an input that isn't really a true LVPECL structure, I ran the signals through LVEP17s first. You use 140 ohm to ground (nice small chip resistors- 0402 if you can) on the LVEP17 outputs and just the 100 ohm internal termination in the FPGA input which is set to LVDS. Worked like a charm at 200 Mbps/MHz with nice crisp transitions. Should work at twice that rate.

 

I know app notes like to show these resistor based shifting arrays, but my experience with those has been less than optimal. And if you have a lot of signals, it's actually easier to lay out a bunch of buffer chips away from the FPGA than to try and place six resistors around each input right at the FPGA. It becomes impossbile even with 0102 resistors and your board layout guy will take out a contract hit on you.