07-31-2007 02:45 AM - edited 07-31-2007 10:54 PM
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Message Edited by wellion990 on 07-31-2007 02:46 AM
Message Edited by wellion990 on 07-31-2007 10:54 PM
09-27-2010 07:16 AM
This message was moved by Xilinx Forum Moderator. If you have any questions, please contact Forum Moderator.
08-15-2012 05:58 AM
I want to ask some questions about xapp879 s6 pll reconfiguration,when I see the output clock of the reference design by chipcsope, I think the output clocks is wrong? But in the xapp879 s6 pll reconfiguration file, the author says that the refrence design is verification in hardware. thank!