- Choose to receive important news and product information
- Gain access to special content
- Personalize your web experience on Xilinx.com

- Xilinx User Community Forums
- Xcell Daily Blog
- General Discussion
- New Users
- General Technical Discussion
- Forum Usage
- Silicon Devices
- Virtex® Family FPGAs
- Spartan® Family FPGAs
- 7 Series FPGAs
- Zynq All Programmable SoC
- CPLDs
- Silicon Devices - Others
- Design Tools
- Vivado TCL Community
- Installation and Licensing
- Design Entry
- HLS
- Simulation and Verification
- Synthesis
- Implementation
- Timing Analysis
- Hierarchical Design
- Design Planning
- Design Tools - Others
- Archived ISE issues
- Embedded Solutions
- Embedded Development Tools
- Embedded Processor System Design
- Embedded Linux
- PicoBlaze
- DSP Solutions
- DSP Tools
- Digital Signal Processing - IP and Algorithms
- Boards and Kits
- Xilinx Boards and Kits
- 3rd Party/Other Boards and Kits
- Intellectual Property
- PCI Express
- Connectivity
- MIG
- System Logic

turn on suggestions

Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.

- Xilinx User Community Forums
- :
- Xilinx Products
- :
- DSP Solutions
- :
- Digital Signal Processing - IP and Algorithms
- :
- FIR core and fixed point notation in the wizard

Topic Options

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic to the Top
- Bookmark
- Subscribe
- Printer Friendly Page

0

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

07-28-2011 06:32 AM - edited 07-28-2011 06:39 AM

When setting up a FIR core, it asks how many bits the input has and how many are fractional bits. The guides talk about this like FIX_15_8 and UFIX_8_8.

But suppose that I have signed 16-bit data which is supposed to be a value between -1 and 1. Does this mean the format would be FIX_16_16? Or FIX_15_15? Or even FIX_16_15?

I generated a FIR core using 16 bits input and told it I had 16 bits for the fractional value. Is this correct, or should this be 16 bit wide input with 15 bits fractional data (as the first bit is a sign bit)?

Solved! Go to Solution.

0

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

07-28-2011 05:34 PM

If the data is in the range of [-1, 1), use FIX_16_15. The fixed point data should be in the 2's complement format.

cyberwizzard wrote:

When setting up a FIR core, it asks how many bits the input has and how many are fractional bits. The guides talk about this like FIX_15_8 and UFIX_8_8.

But suppose that I have signed 16-bit data which is supposed to be a value between -1 and 1. Does this mean the format would be FIX_16_16? Or FIX_15_15? Or even FIX_16_15?

I generated a FIR core using 16 bits input and told it I had 16 bits for the fractional value. Is this correct, or should this be 16 bit wide input with 15 bits fractional data (as the first bit is a sign bit)?

Cheers,

Jim

Jim

0

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

08-15-2011 05:19 AM - edited 08-15-2011 05:20 AM

Thanks for the clarification.

Since the result is 2's complement (like the input), am I correct in assuming the result (without integer components, which should be zero) can be reassembled into signed 16-bit (FIX_16_15) by using the first bit for the sign, followed by the first 15 bits of the fractional part?

If so, I am wondering why I get a DC offset from the filters...

0

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

08-16-2011 04:56 AM

The output is in 2's complement as well. There is no need to reassemble.

cyberwizzard wrote:

Thanks for the clarification.

Since the result is 2's complement (like the input), am I correct in assuming the result (without integer components, which should be zero) can be reassembled into signed 16-bit (FIX_16_15) by using the first bit for the sign, followed by the first 15 bits of the fractional part?

If so, I am wondering why I get a DC offset from the filters...

Cheers,

Jim

Jim

0

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

08-16-2011 01:43 PM

Perhaps I used the wrong wording.

My input is FIX_16_15 and since the filter coefficients should prevent an integer result, I want a FIX_16_15 result from the FIR filter.

Since the output is something like FIX_58_48 due to bit growth, I was planning on using the first bit and the first 15 fractional bits to create a FIX_16_15 result again (similar to the input). But since I'm not getting the expected results I was wondering if that idea was wrong.

On the other hand, if I could force the FIR generator to create FIX_16_15 output in the first place that would suffice as well.