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Contributor
xilinx_user9
Posts: 49
Registered: ‎05-09-2008
0
Accepted Solution

EDK 10.1 SP2 & Chipscope

Hello,

 

 I had a design compiled fine with EDK 10.1 SP1. With EDK 10.1 SP2, I've got the following error message.

 

Running synthesis...

bash -c "cd synthesis; ./synthesis.sh"

xst -ifn system_xst.scr -intstyle silent

Running XST synthesis ...

ERROR:Xst:1617 - Processing TIMESPEC TS_U_TO_D: user TIMEGRP 'D_CLK' must be previously defined in FROM/TO constraint.

ERROR:Xst:1489 - Constraint annotation failed.

make: *** [implementation/system.ngc] Error 1

ERROR:MDT - Error while running "make -f system.make netlist"

No changes to be saved in MSS file

No changes to be saved in XMP file

ERROR: synthesizing XPS module failed!

Process "XPS Process: Synthesize XPS Source" failed

 

Note : my design have a system.xmp instantiated in the top vhdl source file. This system.xmp contains an chipscope icon, with control0 as an external port : I want to use chipscope to debug my vhdl design AND use xmd (target is Spartan3A).

In fact, Xilinx software produced a wrong ncf file with wrong timespec

I think that is fairly common approach and I'm almost surprised not to see similar message in the forum

 

I 've already open a webcase for this (big) bug (first time, for many years I used Xilinx software, I need to go back to a previous SP…). The solution was to go back to SP1.

 

I'm a bit worry because I see no answer record concerning it. Is there any patch ? other solution ? or, a least, is it solved in EDK SP3 ?

Thanks in advance for your response.

 

Best regards.

Expert Contributor
golson
Posts: 898
Registered: ‎04-07-2008
0

Re: EDK 10.1 SP2 & Chipscope

 

 Don't mean to get Xilinx off the hook for problems with synthesizing your Chipscope components however there is another way to use

chipscope which may avoid these problems described.

 

There is a alternative approach to using chipscope with EDK that has worked for me with a Virtex 5 chip.

 

You can try this if you want I recommend theses links.

 

http://www.xilinx.com/support/documentation/ip_documentation/ug241.pdf

http://forums.xilinx.com/xlnx/board/message?board.id=EDK&message.id=2795#M2795

http://www.xilinx.com/support/answers/19423.htm

 

 

especially the 19423 link.

 

In a nutshell here is a simplified procedure:

 

Go to the menu and select hardware -> generate netlists

 

After the netlist has been built then type

go into the implementation directory and type

 

ngcbuild -i system.ngc system_all.ngc

 

after ngcbuild has completed then bring up Chipscope inserter:

 

 

have the input selected as system_all.ngc

and the output selected as system.ngc

 

 Make sure you disable RPM radio button.  and you choose the correct type of Chip family such as virtex 5.

 

Then accept these changes by selecting next or whatever.

 

Then configure your chipscope  selecting signals and clock and how many signals for the ILA ect.

 

After configured.  Save your CDC file with a arbitrary name and allow chipscope inserter to run through.

 

It will insert the ILA ect into your design.

 

After ILA has been added to the design by chipscope inserter.

 

Do the following:

 

Hardware -> Generate Bitstream

 

After bitstream has been generated.

 

Download to the Board the bitstream

Bring up XMD download and connect the application software to the board

 

So that the microblaze is up and running

 

Bring up Chipscope analyzer (a different software)

 

Connect Cable that is get JTAG communication with board running.

 

Start Using Chipscope.

 

This procedure is illustrated at

 

http://www.xilinx.com/support/answers/19423.htm

 

 

 

 

 

Contributor
xilinx_user9
Posts: 49
Registered: ‎05-09-2008
0

Re: EDK 10.1 SP2 & Chipscope

Hello,

 

Thanks you for your long answer. I will examined it in details. I use system.xmp with ISE (instanciated component), so I will read your hyperlink if I can adapt it to ISE.

However... I'd prefered not use core inserter, simply use what I've done with ISE 10.1 SP1 (and ISE 10.1, 9.2 with all SP) ! So I greatly appreciated to have a Xilinx answer told me that this bug has been solved.

 

Regards.

Xilinx Employee
Chadn_na
Posts: 290
Registered: ‎08-15-2007
0

Re: EDK 10.1 SP2 & Chipscope

I would recommend opening a webcase as it is hard to tell with out looking at the files what the problem might be...

Contributor
xilinx_user9
Posts: 49
Registered: ‎05-09-2008
0

Re: EDK 10.1 SP2 & Chipscope

Hello,

 

Thanks for your answer. I've already open a Webcase for this problem, as I wrote in the first post. It has been "closed" with the solution to go back to SP1. However, I hope Xilinx people works to solve this bug. This is the aim of this thread.

 

Regards.

Xilinx Employee
Chadn_na
Posts: 290
Registered: ‎08-15-2007
0

Re: EDK 10.1 SP2 & Chipscope

[ Edited ]

Can you post your project or a test project on the FTP site and post the name of the zip file here:

http://www.xilinx.com/support/answers/1368.htm

I can then see what is going on...

Message Edited by chadn on 08-18-2008 07:59 AM
Contributor
xilinx_user9
Posts: 49
Registered: ‎05-09-2008
0

Re: EDK 10.1 SP2 & Chipscope

Hello,

 

Thanks taking into account this problem.

I've upload a project showing this problem. The name is "ML505_MB_XMK_10_1.zip", 2Mo. This project came from a Xilinx example and I've just add Chipscope icon IP with "control0" as an external port. This project (ML505_MB_XMK_10_1.zip) works fine with EDK SP1 but fails with EDK SP2. The message is:

ERROR:Xst:1617 - Processing TIMESPEC TS_U_TO_D: user TIMEGRP 'D_CLK' must be previously defined in FROM/TO constraint.
ERROR:Xst:1489 - Constraint annotation failed.
make: *** [implementation/system.ngc] Error 1

 

Note: I've used FireFTP and I've the following message (I can't see my file, I repeat the steps many times and hope the file was, in fact upload...).

227 Entering Passive Mode (63,241,181,136,128,22)
       STOR ML505_MB_XMK_10_1.zip
150 Ok to send data.
226 File receive OK.
       TYPE A
200 Switching to ASCII mode.
       PASV
227 Entering Passive Mode (63,241,181,136,128,24)
       LIST
150 Here comes the directory listing.
226 Transfer done (but failed to open directory).
       NOOP
200 NOOP ok.

 

 

Best regards.

Xilinx Employee
Chadn_na
Posts: 290
Registered: ‎08-15-2007
0

Re: EDK 10.1 SP2 & Chipscope

[ Edited ]

If you look in the following folder you will find an ncf file, these constraints are getting added to the Chipscope core.  XST is correct in erroring out since you do not have a D_CLK group defined.  The D_CLK group is typically defined in a ILA or IBA core. 

$PROJECT_NAME\implementation\chipscope_icon_0_wrapper

I compared the differences between 10.1.01i and 10.1.02i and traced it the following line in the Chipscope tcl file:

# exec rm -f [file nativename [pwd]]/implementation/$params(INSTANCE)_wrapper/$params(INSTANCE).ncf

The file can be found at:

$XILINX_EDK\hw\XilinxProcessorIPLib\pcores\chipscope_icon_v1_02_a\data

Basically the ncf file is not getting added to the folder above in 10.1.01 (this line is uncommented in 10.1.01i and commented in 10.1.02i), hence you were not seeing this error in 10.1.01i. 

You have three options:

uncomment this line in the tcl (so ncf file is not added)

add an ILA or IBA to your EDK project (will add d_clk group)

Move the ICON core to your ISE project

 

Is there a particular reason why you are adding the ICON to the EDK project if you are attaching to it in your ISE portion?  I am not sure why that line was changed (uncommented/commented) but I think typically is was expected that if you were using the ICON core in EDK you would be using an ILA, IBA, or VIO so the D_CLK would be defined.

 

Message Edited by chadn on 08-18-2008 01:05 PM
Xilinx Employee
Chadn_na
Posts: 290
Registered: ‎08-15-2007
0

Re: EDK 10.1 SP2 & Chipscope

After you reading your initial description I can see why you are including ICON in EDK.

If you have one BSCAN block (ie S3, V2P, and other devices), including the ICON in EDK can make it easier because you do not need to port the JTAG signals from the ISE portion to the EDK portion (since EDK will automatically hook up the JTAG signals from the ICON to the MDM).  I have filed a CR so developers are aware of this...

However, if you are using V-5 device which has multiple BSCAN blocks I do not really see any advantages of including the ICON block in the EDK portion of the design and would recommend you move it the ISE portion.

 

Contributor
xilinx_user9
Posts: 49
Registered: ‎05-09-2008
0

Re: EDK 10.1 SP2 & Chipscope

Hello,

 

Thanks you very much for this solution, Now it's work ! I will try today on my original design and tell you if it's ok (probably yes)
Strange to see on the line above :
"
## TODO : See what the NCF error is
"
Anyway, yes my target is Spartan-3A and I want to use mdm to download my software and use Chipscope ila core in my vhdl design to debug logic.
I remember, in previous release of ISE (and without EDK), sometimes, I've got same kind of problem with the generated ncf file (from Chipscope Generator) and
I deleted it manually and it worked. Here, I've also try to delete manually ncf file in \implementation\chipscope_icon_0_wrapper but it wasn't work.

Thanks again for your support (I can re-install EDK SP2) and filling an CR.

Best regards.