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Visitor
pradeepkumar481
Posts: 16
Registered: ‎10-07-2009
0
Accepted Solution

Generating SIne Wave

Hello Friends,

I am a newbie.. hope you dont mind if my query is odd..

i wanted to the know like how can we generate a SINE WAVE.. by writing a verilog or vhdl code.

i browsed through some online material, and what i got to know is, one best possible way is using look up table. but when i generate the look up table( i used excel sheet and using these values as a text file), i cant read that LUT as a text since it holds fractions(floating point values) how to avoid this problem and any other method for generating sine wave.

Thanks in advance
Pradeep
 
Super Contributor
sridar
Posts: 200
Registered: ‎09-20-2007
0

Re: Generating SIne Wave

Hi,

If you meant to implement the sine wave generation in FPGA then it is not possible, Because FPGA is digital device basically. One thing is you can store the contents in FPGA and send it to the external DAC which will produce sine wave. This can be done easily using VHDL or verilog or you can look at the DDS core available from xilinx

FPGA freak
Super Contributor
ninjamafiakhan3
Posts: 157
Registered: ‎07-06-2008
0

Re: Generating SIne Wave

You can only generate 1s and 0s (digital logic's equivalent of two different voltage levels) within the FPGA device itself. However a Digital to Analog Converter (DAC) can help you with your task. You can represent negative numbers using 1s  and 0s with the help of 2's complement or 1's complement representation techniques. 2's complement is more widely used because of several reasons. Then you generate your lookup table (using suitable step-size/resolution) accordingly and feed the output to a DAC with proper offset and amplitude settings to get your required waveform.
Visitor
pradeepkumar481
Posts: 16
Registered: ‎10-07-2009
0

Re: Generating SIne Wave

Thank you sridar & ninjamafiakhan3 for your prompt response, i will look in to the information as what you have given me..but if i dont get any clarity then can you help me furthur probably with any code..

 

and can you help me with these queriesagain

 

1) how can we read the values stored in text as DECIMALS into FPGA..i know how to read hex values from text using

 

 reg [31:0] Mem [0:3599];
 initial
 $readmemh("sine.txt",Mem); ==>> this reads values stored in sine.txt as only hex how can i read them in decimal format directly

 

2) i am attaching the sine.txt which i generated using excel sheet..

 


 

i have taken some 3600 samples of sine wave i.e, 2*pi/3600 and for each of that value i have taken sine values and stored here and i thought, i can read these sine values in to fpga and display out the values, only (3) is stored as sine.txt (1) (2) (3) S.No 2*Pi/3600 Sin((2*Pi/3600)*S.No) 1 0.001745329 0.001745328 2 0.003490659 0.003490651 3 0.005235988 0.005235964 4 0.006981317 0.00698126 5 0.008726646 0.008726535 6 0.010471976 0.010471784 7 0.012217305 0.012217001 8 0.013962634 0.01396218 9 0.015707963 0.015707317 10 0.017453293 0.017452406 11 0.019198622 0.019197442 12 0.020943951 0.02094242 13 0.02268928 0.022687334 14 0.02443461 0.024432178 15 0.026179939 0.026176948 16 0.027925268 0.027921639 17 0.029670597 0.029666244 18 0.031415927 0.031410759 19 0.033161256 0.033155178 20 0.034906585 0.034899497 21 0.036651914 0.036643709 22 0.038397244 0.038387809 23 0.040142573 0.040131793 24 0.041887902 0.041875654 25 0.043633231 0.043619387 26 0.045378561 0.045362988 27 0.04712389 0.047106451 28 0.048869219 0.04884977 29 0.050614548 0.05059294 30 0.052359878 0.052335956 31 0.054105207 0.054078813 32 0.055850536 0.055821505 33 0.057595865 0.057564027 34 0.059341195 0.059306374 35 0.061086524 0.06104854 36 0.062831853 0.06279052 37 0.064577182 0.064532308 38 0.066322512 0.0662739 39 0.068067841 0.068015291 40 0.06981317 0.069756474 41 0.071558499 0.071497444 42 0.073303829 0.073238197 43 0.075049158 0.074978727 44 0.076794487 0.076719028 45 0.078539816 0.078459096 46 0.080285146 0.080198924 47 0.082030475 0.081938509 48 0.083775804 0.083677843 49 0.085521133 0.085416923 50 0.087266463 0.087155743 51 0.089011792 0.088894297 52 0.090757121 0.09063258 53 0.09250245 0.092370587 54 0.09424778 0.094108313 55 0.095993109 0.095845753 56 0.097738438 0.0975829 57 0.099483767 0.09931975 58 0.101229097 0.101056297 59 0.102974426 0.102792537 60 0.104719755 0.104528463 61 0.106465084 0.106264071 62 0.108210414 0.107999356 63 0.109955743 0.109734311 64 0.111701072 0.111468932 65 0.113446401 0.113203214 66 0.115191731 0.11493715 67 0.11693706 0.116670737 68 0.118682389 0.118403968 69 0.120427718 0.120136839 70 0.122173048 0.121869343 71 0.123918377 0.123601477 72 0.125663706 0.125333234 73 0.127409035 0.127064609 74 0.129154365 0.128795597 75 0.130899694 0.130526192 76 0.132645023 0.13225639 77 0.134390352 0.133986185 78 0.136135682 0.135715572 79 0.137881011 0.137444546 80 0.13962634 0.139173101 81 0.141371669 0.140901232 82 0.143116999 0.142628934 83 0.144862328 0.144356201 84 0.146607657 0.146083029 85 0.148352986 0.147809411 86 0.150098316 0.149535343 87 0.151843645 0.15126082 88 0.153588974 0.152985836 89 0.155334303 0.154710386 90 0.157079633 0.156434465 91 0.158824962 0.158158067 92 0.160570291 0.159881188 93 0.16231562 0.161603821 94 0.16406095 0.163325962 95 0.165806279 0.165047606 96 0.167551608 0.166768747 97 0.169296937 0.16848938 98 0.171042267 0.170209499 99 0.172787596 0.1719291 100 0.174532925 0.173648178 101 0.176278254 0.175366726 102 0.178023584 0.17708474 103 0.179768913 0.178802215 104 0.181514242 0.180519145 105 0.183259571 0.182235525 106 0.185004901 0.183951351 107 0.18675023 0.185666615 108 0.188495559 0.187381315 109 0.190240888 0.189095443 110 0.191986218 0.190808995 111 0.193731547 0.192521967 112 0.195476876 0.194234351 . . . . . . extended to 3600 samples

 

as i told you i cant read this fractional values into fpga.

 

Mr.Sridar you replied me that i should read the values into fpga and use DAC..i guess i am wrong here but could please tell me how to read these(ex: 0.001745328) type of values into fpga which command is useful

 

i hope i will get a reply soon
Super Contributor
ninjamafiakhan3
Posts: 157
Registered: ‎07-06-2008
0

Re: Generating SIne Wave

Thats a fine sine wave you are trying to generate. How many bits DAC are you going to use?

Like say want to write the value +0.001745328 into the FPGA. Store instead 1745328 (positive) using a 2's complement n bits representation..where you will need to calculate the value of n...which in your case will be large and you might not have access to an n bit DAC...

Might I ask why you want to generate a sine wave with 3600 samples per period? What will be its frequency? Generally 10-20 samples per period are enough to produce very accurate results...

Visitor
pradeepkumar481
Posts: 16
Registered: ‎10-07-2009
0

Re: Generating SIne Wave

Thank you ninjamafiakhan3, for your valuable input..  i feel i am at very basic level of programming, as you have advised i have taken 20 samples of it as you can see below

as you have said i have taken 2*pi/20 and completed 20 samples i converted them into integers upto 3 digits and took 2's compliment 2*pi/20 Sin((2*Pi/3600)*S.No) I2 * 1000 INT(J2) 2's Compliment 1) 0.314159265 0.309016994 309.0169944 309 0100110101 2) 0.628318531 0.587785252 587.7852523 587 1001001011 3) 0.942477796 0.809016994 809.0169944 809 1100101001 4) 1.256637061 0.951056516 951.0565163 951 1110110111 5) 1.570796327 1 1000 1000 1111101000 6) 1.884955592 0.951056516 951.0565163 951 1110110111 7) 2.199114858 0.809016994 809.0169944 809 1100101001 8) 2.513274123 0.587785252 587.7852523 587 1001001011 9) 2.827433388 0.309016994 309.0169944 309 0100110101 10)3.141592654 3.67523E-15 0 0 0 11)3.455751919 -0.309016994 -309.0169944 -310 0011001010 12)3.769911184 -0.587785252 -587.7852523 -588 0110110100 13)4.08407045 -0.809016994 -809.0169944 -810 0011010110 14)4.398229715 -0.951056516 -951.0565163 -952 0001001000 15)4.71238898 -1 -1000 -1000 0000011000 16)5.026548246 -0.951056516 -951.0565163 -952 0001001000 17)5.340707511 -0.809016994 -809.0169944 -810 0011010110 18)5.654866776 -0.587785252 -587.7852523 -588 0110110100 19)5.969026042 -0.309016994 -309.0169944 -310 0011001010 20)6.283185307 -7.35046E-15 -7.35046E-12 0 0

 

does this work, 

also as u asked the kind of DAC what we r having is  12 bit DAC , but before that i just wanted to display (probabily plot sinewave) using these values.. so can i read the above binary values using $readmemb command

and also later how can i tell simulator that i have negative numbers..please can you help me with this situation.. i think you can understand that i am a newbiein programming.

 

if i am wrong in any way can you suggest me more.

waiting for your reply 

Thanks in advance

Pradeep

Expert Contributor
eilert
Posts: 2,386
Registered: ‎08-14-2007
0

Re: Generating SIne Wave

[ Edited ]

Hi all,

a wave table is not really necessary.

As a reply to an article in antti-brain sep. 2009 (http://groups.google.com/group/antti-brain/files?hl=en)

I wrote this little Testbench which contains a process that generates a sine wave.

The initial values are fixed point representations in std_logic_vector format. 

It uses just one multiplier and an adder/subtractor, but see for yourself:

 

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;

ENTITY tb_simplesine IS
END tb_simplesine;

ARCHITECTURE testbench OF tb_simplesine IS

SIGNAL alpha : std_logic_vector(23 DOWNTO 0);
SIGNAL beta : std_logic_vector(23 DOWNTO 0);
--SIGNAL mult : std_logic_vector(47 DOWNTO 0);
--SIGNAL n1 : std_logic_vector(23 DOWNTO 0);
--SIGNAL n2 : std_logic_vector(23 DOWNTO 0);
--SIGNAL sine : std_logic_vector(23 DOWNTO 0);

SIGNAL reset : std_logic;
SIGNAL clock : std_logic;
SIGNAL simulation_done : boolean := false;
SIGNAL load : std_logic;

BEGIN -- testbench

-- purpose: simple sine wave generator
-- type : sequential
-- inputs : clock, reset, alpha, beta
-- outputs: sine
sinegen: PROCESS (clock, reset)
VARIABLE alfa : std_logic_vector(23 DOWNTO 0);
VARIABLE mult : std_logic_vector(47 DOWNTO 0);
variable n1 : std_logic_vector(23 DOWNTO 0);
variable n2 : std_logic_vector(23 DOWNTO 0);
VARIABLE sine : std_logic_vector(23 DOWNTO 0);

BEGIN -- PROCESS sinegen
IF reset = '0' THEN -- asynchronous reset (active low)
mult := (OTHERS => '0');
sine := (OTHERS => '0');
n1 := (OTHERS => '0');
n2 := (OTHERS => '0');
alfa := (OTHERS => '0');

ELSIF clock'event AND clock = '1' THEN -- rising clock edge
IF load='1' THEN
n2 := beta; --use in port later
alfa := alpha; --use in port later
ELSE
mult := alfa * n1;
sine := mult(45 DOWNTO 45-24) - n2;
n2 := n1;
n1 := sine;
END IF;

END IF;
END PROCESS sinegen;

-- purpose: generate clocks
-- type : combinational
-- inputs :
-- outputs: clock
clock_gen: PROCESS
BEGIN -- PROCESS clock_gen
IF NOT simulation_done THEN
clock <= '1';
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
ELSE
wait;
END IF;
END PROCESS clock_gen;

-- purpose: test the algorithm above
-- type : sequential
-- inputs : clock
-- outputs:
testrun: PROCESS
BEGIN -- PROCESS testrun
reset <= '1';
load <= '0';
alpha <= B"01_1111111011100111010110"; -- 1_9957177 24 bit fixedpoint
beta <= B"11_1110111101000001110000"; -- -_065403
WAIT until clock'event AND clock = '1' ;
WAIT until clock'event AND clock = '1' ;
WAIT until clock'event AND clock = '0' ;
reset <= '0';
load <= '1';
WAIT until clock'event AND clock = '1' ;
WAIT until clock'event AND clock = '1' ;
load <= '0';
FOR i IN 0 TO 400 LOOP
WAIT until clock'event AND clock = '1' ;
END LOOP; -- i
simulation_done <= true;
wait;

END PROCESS testrun;

END testbench;

 

 And in modelsim you can nicely view the sine waves using format/analog (automatic)

Have a nice simulation
  Eilert

 

Message Edited by eilert on 11-04-2009 08:09 AM
Super Contributor
sridar
Posts: 200
Registered: ‎09-20-2007
0

Re: Generating SIne Wave

If you mean to realize the sine wave generation using hardware with FPGA, the flow may be like this.

1. select the DAC chip and calculate the binary values to be given to the DAC (Refer the DAC datasheet).

2. Pre-store these values in FPGA hardware, you can use BRAM or Look-up table kind of architecture using HDL.

3. Send these values to the DAC on every clock edge.

4. Check the output of DAC.

If u agreed or satisfied with this, I can write and send the code for you. 

FPGA freak
Visitor
pradeepkumar481
Posts: 16
Registered: ‎10-07-2009
0

Re: Generating SIne Wave

Thank you Mr. eilert  :smileyvery-happy: & Sridar :smileyvery-happy:  for your valuable reply.

 

Mr. Eilert i went through your code..but dint understand fully the logic  what you used to generate..sorry to say that coz i am a newbie..i will be looking into it again, i request you, if it is possible can you explain the code..

 

also

 

Mr.Sridar can you please send the code..i think it will be helpful for me as i wanted to implement it through hardware..

 

and please do post inputs as how i should procede if iam wrong any where..

 

Thanks in advance :smileyvery-happy:

Pradeep

Expert Contributor
eilert
Posts: 2,386
Registered: ‎08-14-2007
0

Re: Generating SIne Wave

Hi Pradeep,

My code example is just a testbench. The part that does all the work is the process sinegen.

You can extract it and put it in a synthesizable model. 

You need to feed the parameters n2 and alfa via a port, constant or signal, depending on what your design needs.

 

Of course the outputs need to be fed to a DAC when you want to generate a real analog signal outside the FPGA.

For the output, you can forward the needed number of bits (MSBs) to the DAC. (Attention! It's a two's complement (signed) value)

 

You may want to reduce the wordlength, to save area (multipliers) or make it faster. Test out what works for you.

Depending on your FPGA try the native width of a single hardware multiplier or DSP-Macro.

 

With the input parameters you can change the output frequency (and/or amplitude and phase)

 

Why it works? Well in the past some cunning oldtimers without TV or mobile phones had nothing better to do than musing about math and funny way's how to calculate a sinewave with the least effort.

This is one of the most simple algorithms. It was developed back in 1958 by Gerald Goertzel.

 

Have a nice synthesis

  Eilert