Don't have a Xilinx account yet?

  • Choose to receive important news and product information
  • Gain access to special content
  • Personalize your web experience on Xilinx.com

Create Account

Username

Password

Forgot your password?
XClose Panel
Xilinx Home
Reply
Newbie
mfpga
Posts: 2
Registered: ‎03-24-2009
0

Implementation Translate Error

To those interested:

 

I ran into the following error (I have alot more constraint system messages, but they are all the same format):

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

ConstraintSystem:59 - Constraint <NET "DQ<15>" LOC= "T1";>
   [gates2_top.ucf(114)]: NET "DQ<15>" not found.  Please verify that:
   1. The specified design element actually exists in the original design.

   2. The specified object is spelled correctly in the constraint source file.

ConstraintSystem:59 - Constraint <NET "PS2C"  LOC = "R12"  ;>
   [gates2_top.ucf(117)]: NET "PS2C" not found.  Please verify that:
   1. The specified design element actually exists in the original design.

   2. The specified object is spelled correctly in the constraint source file.

ConstraintSystem:59 - Constraint <NET "PS2D"  LOC = "P11"  ;>
   [gates2_top.ucf(118)]: NET "PS2D" not found.  Please verify that:
   1. The specified design element actually exists in the original design.

   2. The specified object is spelled correctly in the constraint source file.

Done...
Checking Partitions ...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:    90
  Number of warnings:   0


One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "gates2_top.bld"...
File 'c:/My_Designs/Example1/gates2/implement/ver1/rev1/gates2_top.ngd' does not exist.
NGDBUILD failed.
Implementation ver1->rev1 Failed.

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 

 

I'm working with the Spartan 3E 1200 FG320 FPGA(part of the Nexys 2 kit from digilent www.digilentinc.com/nexys2).  I am using the Learning by Example Using VHDL from www.lbebooks.com.  These have been great so far in teaching myself VHDL.

 

Does anyone know why this is occuring, or why the .ngd file isn't being created?  I followed the path to where it "should" be located and it isn't there, so I am assuming that it gets created in an earlier stage.  Attached is the entire log.

 

 

Thank you

Newbie
mfpga
Posts: 2
Registered: ‎03-24-2009
0

Re: Implementation Translate Error

I was able to correct this error,  the .ucf file from www.lbebooks.com contains a netlist of all i/o's.

I had to delete the ones not in use(my program is simple, so I didn't need to many of those).

I now realize I was spoiled by getting that .ucf file created for me, but keeping the .ucf file clean and to only what you need is better practice